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GD32F450VGT6

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GigaDevice Semicon Beijing Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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GD32F450VGT6

GigaDevice Semicon Beijing · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)

GD32F450VGT6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V tolerant I/O, default PE2; alternate functions TRACECLK, SPI3_SCK, ETH_MII_TXD3, EXMC_A23, EVENTOUT.
2 PE3 bidirectional 5 V tolerant I/O, default PE3; alternate functions TRACED0, EXMC_A19, EVENTOUT.
3 PE4 bidirectional 5 V tolerant I/O, default PE4; alternate functions TRACED1, SPI3_NSS, EXMC_A20, DCI_D4, TLI_B0, EVENTOUT.
4 PE5 bidirectional 5 V tolerant I/O, default PE5; alternate functions TRACED2, TIMER8_CH0, SPI3_MISO, EXMC_A21, DCI_D6, TLI_G0, EVENTOUT.
5 PE6 bidirectional 5 V tolerant I/O, default PE6; alternate functions TRACED3, TIMER8_CH1, SPI3_MOSI, EXMC_A22, DCI_D7, TLI_G1, EVENTOUT.
6 VBAT power_in Default function VBAT; power pin listed in the pin definitions table.
7 PC13-TAMPER-RTC bidirectional 5 V tolerant I/O, default PC13; alternate EVENTOUT; additional RTC_TAMP0, RTC_OUT, RTC_TS.
8 PC14-OSC32IN bidirectional 5 V tolerant I/O, default PC14; alternate EVENTOUT; additional function OSC32IN.
9 PC15-OSC32OUT bidirectional 5 V tolerant I/O, default PC15; alternate EVENTOUT; additional function OSC32OUT.
10 VSS power_in Ground pin, default VSS.
11 VDD power_in Power supply pin, default VDD.
12 PH0-OSC_IN bidirectional 5 V tolerant I/O, default PH0 and OSCIN; alternate EVENTOUT; additional function OSCIN.
13 PH1-OSC_OUT bidirectional 5 V tolerant I/O, default PH1 and OSCOUT; alternate EVENTOUT; additional function OSCOUT.
14 NRST input Default function NRST, the device reset pin.
15 PC0 bidirectional 5 V tolerant I/O, default PC0; alternate USBHS_ULPI_STP, EXMC_SDNWE, EVENTOUT; additional ADC012_IN10.
16 PC1 bidirectional 5 V tolerant I/O, default PC1; alternate SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, ETH_MDC, EVENTOUT; additional ADC012_IN11.
17 PC2 bidirectional 5 V tolerant I/O, default PC2; alternate SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, ETH_MII_TXD2, EXMC_SDNE0, EVENTOUT; additional ADC012_IN12.
18 PC3 bidirectional 5 V tolerant I/O, default PC3; alternate SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, ETH_MII_TX_CLK, EXMC_SDCKE0, EVENTOUT; additional ADC012_IN13.
19 VDD power_in Power supply pin, default VDD.
20 VSSA power_in Analog ground pin, default VSSA.
21 VREF+ power_in Analog reference voltage pin, default VREF+.
22 VDDA power_in Analog power supply pin, default VDDA.
23 PA0-WKUP bidirectional 5 V tolerant I/O, default PA0; alternate TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, ETH_MII_CRS, EVENTOUT; additional ADC012_IN0 and WKUP.
24 PA1 bidirectional 5 V tolerant I/O, default PA1; alternate TIMER1_CH1, TIMER4_CH1, SPI3_MOSI, USART1_RTS, UART3_RX, ETH_MII_RX_CLK, ETH_RMII_REF_CLK, EVENTOUT; additional ADC012_IN1.
25 PA2 bidirectional 5 V tolerant I/O, default PA2; alternate TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, ETH_MDIO, EVENTOUT; additional ADC012_IN2.
26 PA3 bidirectional 5 V tolerant I/O, default PA3; alternate TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, ETH_MII_COL, TLI_B5, EVENTOUT; additional ADC012_IN3.
27 VSS power_in Ground pin, default VSS.
28 VDD power_in Power supply pin, default VDD.
29 PA4 bidirectional Analog-tolerant I/O (TTa), default PA4; alternate SPI0_NSS, SPI2_NSS, I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, TLI_VSYNC, EVENTOUT; additional ADC01_IN4 and DAC_OUT0.
30 PA5 bidirectional Analog-tolerant I/O (TTa), default PA5; alternate TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT; additional ADC01_IN5 and DAC_OUT1.
31 PA6 bidirectional 5 V tolerant I/O, default PA6; alternate TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, TLI_G2, EVENTOUT; additional ADC01_IN6.
32 PA7 bidirectional 5 V tolerant I/O, default PA7; alternate TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, ETH_MII_RX_DV, ETH_RMII_CRS_DV, EXMC_SDNWE, EVENTOUT; additional ADC01_IN7.
33 PC4 bidirectional 5 V tolerant I/O, default PC4; alternate ETH_MII_RXD0, ETH_RMII_RXD0, EXMC_SDNE0, EVENTOUT; additional ADC01_IN14.
34 PC5 bidirectional 5 V tolerant I/O, default PC5; alternate USART2_RX, ETH_MII_RXD1, ETH_RMII_RXD1, EXMC_SDCKE0, EVENTOUT; additional ADC01_IN15.
35 PB0 bidirectional 5 V tolerant I/O, default PB0; alternate TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, SPI4_SCK, SPI2_MOSI, I2S2_SD, TLI_R3, USBHS_ULPI_D1, ETH_MII_RXD2, SDIO_D1, EVENTOUT; additional ADC01_IN8 and IREF.
36 PB1 bidirectional 5 V tolerant I/O, default PB1; alternate TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, SPI4_NSS, TLI_R6, USBHS_ULPI_D2, ETH_MII_RXD3, SDIO_D2, EVENTOUT; additional ADC01_IN9.
37 PB2 bidirectional 5 V tolerant I/O, default PB2 and BOOT1; alternate TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT.
38 PE7 bidirectional 5 V tolerant I/O, default PE7; alternate TIMER0_ETI, UART6_RX, EXMC_D4, EVENTOUT.
39 PE8 bidirectional 5 V tolerant I/O, default PE8; alternate TIMER0_CH0_ON, UART6_TX, EXMC_D5, EVENTOUT.
40 PE9 bidirectional 5 V tolerant I/O, default PE9; alternate TIMER0_CH0, EXMC_D6, EVENTOUT.
41 PE10 bidirectional 5 V tolerant I/O, default PE10; alternate TIMER0_CH1_ON, EXMC_D7, EVENTOUT.
42 PE11 bidirectional 5 V tolerant I/O, default PE11; alternate TIMER0_CH1, SPI3_NSS, SPI4_NSS, EXMC_D8, TLI_G3, EVENTOUT.
43 PE12 bidirectional 5 V tolerant I/O, default PE12; alternate TIMER0_CH2_ON, SPI3_SCK, SPI4_SCK, EXMC_D9, TLI_B4, EVENTOUT.
44 PE13 bidirectional 5 V tolerant I/O, default PE13; alternate TIMER0_CH2, SPI3_MISO, SPI4_MISO, EXMC_D10, TLI_DE, EVENTOUT.
45 PE14 bidirectional 5 V tolerant I/O, default PE14; alternate TIMER0_CH3, SPI3_MOSI, SPI4_MOSI, EXMC_D11, TLI_PIXCLK, EVENTOUT.
46 PE15 bidirectional 5 V tolerant I/O, default PE15; alternate TIMER0_BRKIN, EXMC_D12, TLI_R7, EVENTOUT.
47 PB10 bidirectional 5 V tolerant I/O, default PB10; alternate TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, ETH_MII_RX_ER, SDIO_D7, TLI_G4, EVENTOUT.
48 PB11 bidirectional 5 V tolerant I/O, default PB11; alternate TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, ETH_MII_TX_EN, ETH_RMII_TX_EN, TLI_G5, EVENTOUT.
49 NC unconnected Pin listed as NC in the LQFP100 pin table; its default function is given as VCORE.
50 VDD power_in Power supply pin, default VDD.
51 PB12 bidirectional 5 V tolerant I/O, default PB12; alternate TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, SPI3_NSS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, ETH_MII_TXD0, ETH_RMII_TXD0, USBHS_ID, EVENTOUT.
52 PB13 bidirectional 5 V tolerant I/O, default PB13; alternate TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, SPI3_SCK, USART2_CTS, CAN1_TX, USBHS_ULPI_D6, ETH_MII_TXD1, ETH_RMII_TXD1, EVENTOUT, I2C1_TXFRAME; additional USBHS_VBUS.
53 PB14 bidirectional 5 V tolerant I/O, default PB14; alternate TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT.
54 PB15 bidirectional 5 V tolerant I/O, default PB15; alternate RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT.
55 PD8 bidirectional 5 V tolerant I/O, default PD8; alternate USART2_TX, EXMC_D13, EVENTOUT.
56 PD9 bidirectional 5 V tolerant I/O, default PD9; alternate USART2_RX, EXMC_D14, EVENTOUT.
57 PD10 bidirectional 5 V tolerant I/O, default PD10; alternate USART2_CK, EXMC_D15, TLI_B3, EVENTOUT.
58 PD11 bidirectional 5 V tolerant I/O, default PD11; alternate USART2_CTS, EXMC_A16, EVENTOUT.
59 PD12 bidirectional 5 V tolerant I/O, default PD12; alternate TIMER3_CH0, USART2_RTS, EXMC_A17, EVENTOUT.
60 PD13 bidirectional 5 V tolerant I/O, default PD13; alternate TIMER3_CH1, EXMC_A18, EVENTOUT.
61 PD14 bidirectional 5 V tolerant I/O, default PD14; alternate TIMER3_CH2, EXMC_D0, EVENTOUT.
62 PD15 bidirectional 5 V tolerant I/O, default PD15; alternate CTC_SYNC, TIMER3_CH3, EXMC_D1, EVENTOUT.
63 PC6 bidirectional 5 V tolerant I/O, default PC6; alternate TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, TLI_HSYNC, EVENTOUT.
64 PC7 bidirectional 5 V tolerant I/O, default PC7; alternate TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, TLI_G6, EVENTOUT.
65 PC8 bidirectional 5 V tolerant I/O, default PC8; alternate TRACED0, TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT.
66 PC9 bidirectional 5 V tolerant I/O, default PC9; alternate CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT.
67 PA8 bidirectional 5 V tolerant I/O, default PA8; alternate CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, TLI_R6, EVENTOUT, CTC_SYNC.
68 PA9 bidirectional 5 V tolerant I/O, default PA9; alternate TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT; additional USBFS_VBUS.
69 PA10 bidirectional 5 V tolerant I/O, default PA10; alternate TIMER0_CH2, SPI4_MOSI, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME.
70 PA11 bidirectional 5 V tolerant I/O, default PA11; alternate TIMER0_CH3, SPI3_MISO, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, TLI_R4, EVENTOUT.
71 PA12 bidirectional 5 V tolerant I/O, default PA12; alternate TIMER0_ETI, SPI4_MISO, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, TLI_R5, EVENTOUT.
72 PA13 bidirectional 5 V tolerant I/O, default JTMS, SWDIO and PA13; alternate EVENTOUT.
73 NC unconnected Pin listed as NC in the LQFP100 pin table with no function given.
74 VSS power_in Ground pin, default VSS.
75 VDD power_in Power supply pin, default VDD.
76 PA14 bidirectional 5 V tolerant I/O, default JTCK, SWCLK and PA14; alternate EVENTOUT.
77 PA15 bidirectional 5 V tolerant I/O, default JTDI and PA15; alternate TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS, I2S2_WS, USART0_TX, EVENTOUT.
78 PC10 bidirectional 5 V tolerant I/O, default PC10; alternate SPI2_SCK, I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, TLI_R2, EVENTOUT.
79 PC11 bidirectional 5 V tolerant I/O, default PC11; alternate I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT.
80 PC12 bidirectional 5 V tolerant I/O, default PC12; alternate I2C1_SDA, SPI2_MOSI, I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT.
81 PD0 bidirectional 5 V tolerant I/O, default PD0; alternate SPI3_MISO, SPI2_MOSI, I2S2_SD, CAN0_RX, EXMC_D2, EVENTOUT.
82 PD1 bidirectional 5 V tolerant I/O, default PD1; alternate SPI1_NSS, I2S1_WS, CAN0_TX, EXMC_D3, EVENTOUT.
83 PD2 bidirectional 5 V tolerant I/O, default PD2; alternate TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT.
84 PD3 bidirectional 5 V tolerant I/O, default PD3; alternate TRACED1, SPI1_SCK, I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5, TLI_G7, EVENTOUT.
85 PD4 bidirectional 5 V tolerant I/O, default PD4; alternate USART1_RTS, EXMC_NOE, EVENTOUT.
86 PD5 bidirectional 5 V tolerant I/O, default PD5; alternate USART1_TX, EXMC_NWE, EVENTOUT.
87 PD6 bidirectional 5 V tolerant I/O, default PD6; alternate SPI2_MOSI, I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10, TLI_B2, EVENTOUT.
88 PD7 bidirectional 5 V tolerant I/O, default PD7; alternate USART1_CK, EXMC_NE0, EXMC_NCE1, EVENTOUT.
89 PB3 bidirectional 5 V tolerant I/O, default JTDO and PB3; alternate TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT.
90 PB4 bidirectional 5 V tolerant I/O, default JNTRST and PB4; alternate TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME.
91 PB5 bidirectional 5 V tolerant I/O, default PB5; alternate TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ETH_PPS_OUT, EXMC_SDCKE1, DCI_D10, EVENTOUT.
92 PB6 bidirectional 5 V tolerant I/O, default PB6; alternate TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, EXMC_SDNE1, DCI_D5, EVENTOUT.
93 PB7 bidirectional 5 V tolerant I/O, default PB7; alternate TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL, DCI_VSYNC, EVENTOUT.
94 BOOT0 bidirectional 5 V tolerant I/O, default function BOOT0.
95 PB8 bidirectional 5 V tolerant I/O, default PB8; alternate TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, SPI4_MOSI, CAN0_RX, ETH_MII_TXD3, SDIO_D4, DCI_D6, TLI_B6, EVENTOUT.
96 PB9 bidirectional 5 V tolerant I/O, default PB9; alternate TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, TLI_B7, EVENTOUT.
97 PE0 bidirectional 5 V tolerant I/O, default PE0; alternate TIMER3_ETI, UART7_RX, EXMC_NBL0, DCI_D2, EVENTOUT.
98 PE1 bidirectional 5 V tolerant I/O, default PE1; alternate TIMER0_CH1_ON, UART7_TX, EXMC_NBL1, DCI_D3, EVENTOUT.
99 VSS power_in Ground pin, default VSS.
100 VDD power_in Power supply pin, default VDD.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Absolute maximum operating temperature range TA -40 85 °C 49
Maximum current for GPIO pins IIO 25 mA 49
Storage temperature range TSTG -55 150 °C 49
Maximum junction temperature TJ 125 °C 49
Input voltage on other I/O VIN 4 V Input voltage on other I/O; min printed as VSS - 0.3 49
Supply voltage VDD 2.6 3.3 3.6 V 50
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 50
Power on reset threshold VPOR 2.3 2.4 2.48 V 52
Power down reset threshold VPDR 1.72 1.8 1.88 V 52
PDR hysteresis VHYST 0.6 V 52
Reset temporization TRSTTEMP 2 ms 52
Electrostatic discharge voltage (human body model) VESD(HBM) 7000 V TA=25 °C; JESD22-A114 52
Electrostatic discharge voltage (charge device model) VESD(CDM) 800 V TA=25 °C; JESD22-C101 52
Static latch-up I-test LU I-test -200 200 mA TA=25 °C; JESD78 52
Supply over voltage latch-up Vsupply 5.4 V Vsupply over voltage 52
High speed external oscillator (HXTAL) frequency fHXTAL 4 8 32 MHz VDD=5.0V 53
HXTAL oscillator duty cycle DHXTAL 30 50 70 % 53
Recommended load capacitance on OSC_IN and OSC_OUT CHXTAL 20 30 pF 53
Low speed external oscillator (LXTAL) load capacitance CLXTAL 15 pF Recommended load capacitance on OSC32_IN and OSC32_OUT 53
LXTAL oscillator duty cycle DLXTAL 30 50 70 % 53
High speed internal oscillator (IRC16M) frequency accuracy, factory-trimmed ACCIRC16M -4 5 % VDD=3.3V, TA=-40°C ~+105°C 54
IRC16M frequency accuracy, factory-trimmed ACCIRC16M -2 2 % VDD=3.3V, TA=0°C ~ +85°C 54
IRC16M frequency accuracy, factory-trimmed ACCIRC16M -1 1 % VDD=3.3V, TA=25°C 54
IRC16M oscillator duty cycle DIRC16M 45 50 55 % VDD=3.3V, fIRC16M=16MHz 54
IRC16M oscillator startup time tSUIRC16M 2.5 4 us VDD=3.3V, fIRC16M=16MHz 54
IRC48M frequency accuracy, factory-trimmed ACCIRC48M -4 5 % VDD=3.3V, TA=-40°C ~+105°C 54
IRC48M frequency accuracy, factory-trimmed ACCIRC48M -3 3 % VDD=3.3V, TA=0°C ~ +85°C 54
IRC48M frequency accuracy, factory-trimmed ACCIRC48M -2 2 % VDD=3.3V, TA=25°C 54
IRC48M oscillator duty cycle DIRC48M 45 50 55 % VDD=3.3V, fIRC48M=16MHz 54
IRC48M oscillator operating current IDDIRC48M 240 300 μA VDD=3.3V, fIRC48M=16MHz 54
Low speed internal oscillator (IRC32K) frequency fIRC32K 20 32 45 KHz VDD=VBAT=3.3V, TA=-40°C ~ +85°C 55
IRC32K oscillator operating current IDDIRC32K 0.4 0.6 μA VDD=VBAT=3.3V, TA=25°C 55
PLL input clock frequency fPLLIN 1 4 MHz 55
PLL output clock frequency fPLL 100 500 MHz 55
Number of guaranteed program/erase cycles before failure (Endurance) PECYC 100 kcycles TA=-40°C ~ +85°C 56
Data retention time tRET 20 years TA=125°C 56
Word programming time tPROG 200 400 us TA=-40°C ~ +85°C 56
Page erase time tERASE 60 100 450 ms TA=-40°C ~ +85°C 56
Mass erase time tMERASE 3.2 9.6 s TA=-40°C ~ +85°C 56
Low level input voltage, standard IO VIL 1.27 V VDD=2.6V 57
High level input voltage, standard IO VIH 1.4 V VDD=2.6V 57
Low level output voltage VOL 0.17 V VDD=2.6V, IIO=8mA 57
High level output voltage VOH 2.39 V VDD=2.6V, IIO=8mA 57
Internal pull-up resistor RPU 30 40 50 kΩ VIN=VSS 57
Internal pull-down resistor RPD 30 40 50 kΩ VIN=VDD 57
ADC operating voltage VDDA 2.6 3.3 3.6 V 58
ADC clock frequency fADC 0.1 40 MHz 58
External input impedance RAIN 52.1 kΩ See Equation 2 58
Input sampling capacitance CADC 5.5 pF No pin/pad capacitance included 58
DAC operating voltage VDDA 2.6 3.3 3.6 V 60
Resistive load RLOAD 5 kΩ Resistive load with buffer ON 60
Impedance output RO 15 kΩ Impedance output with buffer OFF 60
Capacitive load CLOAD 50 pF Capacitive load with buffer ON 60
DC current consumption in quiescent mode, worst code IDDA 560 μA Worst code on the input 60
SCK clock frequency (SPI) fSCK 30 MHz 61

CAD (KiCad official)

  • Symbol: GD32F450VGT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: gd32f450vgt6-etched.step / gd32f450vgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f450vgt6.step / gd32f450vgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (66 pp, sha256 915c24a1f84de32a, retrieved 2026-10-27, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus off (skipped (clean text read)), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF