component

GD32F427VET6

Public Made by Adom

by adom

GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersgd32f427vet6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 8d ago
viewers gd32f427vet6: viewers · Ray 8d ago
gd32f427vet6-etched.glb Publish 0.1.0 · Ray 8d ago
gd32f427vet6-etched.step gd32f427vet6: factory component page (tier=lcsc) · Ray 8d ago
gd32f427vet6-hero.glb gd32f427vet6: hero GLB from the etched model (keeps the MPN mark) · Ray 8d ago
gd32f427vet6-hero.overlay.json Publish 0.1.0 · Ray 8d ago
gd32f427vet6.glb Publish 0.1.0 · Ray 8d ago
gd32f427vet6.kicad_mod Publish 0.1.0 · Ray 8d ago
gd32f427vet6.kicad_sym Publish 0.1.0 · Ray 8d ago
gd32f427vet6.lbr Publish 0.1.0 · Ray 8d ago
gd32f427vet6.step Publish 0.1.0 · Ray 8d ago
package.json Publish 0.1.0 · Ray 8d ago
page.json Set visibility: public · Ray 8d ago
README.md Publish 0.1.0 · Ray 8d ago

GD32F427VET6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F427VET6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional Default GPIO PE2, 5 V tolerant (5VT); alternates ENET_MII_TXD3, EXMC_A23, EVENTOUT.
2 PE3 bidirectional Default GPIO PE3, 5 V tolerant (5VT); alternates EXMC_A19, EVENTOUT.
3 PE4 bidirectional Default GPIO PE4, 5 V tolerant (5VT); alternates EXMC_A20, DCI_D4, EVENTOUT.
4 PE5 bidirectional Default GPIO PE5, 5 V tolerant (5VT); alternates TIMER8_CH0, EXMC_A21, DCI_D6, EVENTOUT.
5 PE6 bidirectional Default GPIO PE6, 5 V tolerant (5VT); alternates TIMER8_CH1, EXMC_A22, DCI_D7, EVENTOUT.
6 VBAT power_in Backup power supply pin (default function VBAT).
7 PC13-TAMPER-RTC bidirectional Default GPIO PC13, 5 V tolerant (5VT); additional RTC_TAMP0, RTC_OUT, RTC_TS; alternate EVENTOUT.
8 PC14-OSC32IN bidirectional Default GPIO PC14, 5 V tolerant (5VT); additional function OSC32IN (low-speed crystal input); alternate EVENTOUT.
9 PC15-OSC32OUT bidirectional Default GPIO PC15, 5 V tolerant (5VT); additional function OSC32OUT (low-speed crystal output); alternate EVENTOUT.
10 VSS power_in Digital ground pin (default function VSS).
11 VDD power_in Digital power supply pin (default function VDD).
12 PH0 bidirectional Default GPIO PH0, 5 V tolerant (5VT); additional function OSCIN (high-speed crystal input); alternate EVENTOUT.
13 PH1 bidirectional Default GPIO PH1, 5 V tolerant (5VT); additional function OSCOUT (high-speed crystal output); alternate EVENTOUT.
14 NRST input Reset pin (default function NRST); NRST pin characteristics are given in datasheet section 4.11. Table lists type as '-', classed here as input.
15 PC0 bidirectional Default GPIO PC0, 5 V tolerant (5VT); alternates USBHS_ULPI_STP, EXMC_SDNWE, EVENTOUT; additional ADC012_IN10.
16 PC1 bidirectional Default GPIO PC1, 5 V tolerant (5VT); alternates SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD, ENET_MDC, EVENTOUT; additional ADC012_IN11.
17 PC2 bidirectional Default GPIO PC2, 5 V tolerant (5VT); alternates SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR, ENET_MII_TXD2, EVENTOUT; additional ADC012_IN12.
18 PC3 bidirectional Default GPIO PC3, 5 V tolerant (5VT); alternates SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT, ENET_MII_TX_CLK, EVENTOUT; additional ADC012_IN13.
19 VDD power_in Digital power supply pin (default function VDD).
20 VSSA power_in Analog ground pin (default function VSSA).
21 VREFP power_in ADC/DAC reference voltage input (default function VREF+).
22 VDDA power_in Analog supply pin; the block diagram shows the SAR ADC and DAC powered from VDDA (default function VDDA).
23 PA0-WKUP bidirectional Default GPIO PA0, 5 V tolerant (5VT); alternates TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI, USART1_CTS, UART3_TX, ENET_MII_CRS, EVENTOUT; additional ADC012_IN0 and WKUP.
24 PA1 bidirectional Default GPIO PA1, 5 V tolerant (5VT); alternates TIMER1_CH1, TIMER4_CH1, USART1_RTS, UART3_RX, ENET_MII_RX_CLK, ENET_RMII_REF_CLK, EVENTOUT; additional ADC012_IN1.
25 PA2 bidirectional Default GPIO PA2, 5 V tolerant (5VT); alternates TIMER1_CH2, TIMER4_CH2, TIMER8_CH0, I2S_CKIN, USART1_TX, ENET_MDIO, EVENTOUT; additional ADC012_IN2.
26 PA3 bidirectional Default GPIO PA3, 5 V tolerant (5VT); alternates TIMER1_CH3, TIMER4_CH3, TIMER8_CH1, I2S1_MCK, USART1_RX, USBHS_ULPI_D0, ENET_MII_COL, EVENTOUT; additional ADC012_IN3.
27 VSS power_in Digital ground pin (default function VSS).
28 VDD power_in Digital power supply pin (default function VDD).
29 PA4 bidirectional Default GPIO PA4; alternates SPI0_NSS, SPI2_NSS/I2S2_WS, USART1_CK, USBHS_SOF, DCI_HSYNC, EVENTOUT; additional ADC01_IN4 and DAC_OUT0. The table gives no 5VT marking for this pin.
30 PA5 bidirectional Default GPIO PA5; alternates TIMER1_CH0, TIMER1_ETI, TIMER7_CH0_ON, SPI0_SCK, USBHS_ULPI_CK, EVENTOUT; additional ADC01_IN5 and DAC_OUT1. The table gives no 5VT marking for this pin.
31 PA6 bidirectional Default GPIO PA6, 5 V tolerant (5VT); alternates TIMER0_BRKIN, TIMER2_CH0, TIMER7_BRKIN, SPI0_MISO, I2S1_MCK, TIMER12_CH0, SDIO_CMD, DCI_PIXCLK, EVENTOUT; additional ADC01_IN6.
32 PA7 bidirectional Default GPIO PA7, 5 V tolerant (5VT); alternates TIMER0_CH0_ON, TIMER2_CH1, TIMER7_CH0_ON, SPI0_MOSI, TIMER13_CH0, ENET_MII_RX_DV, ENET_RMII_CRS_DV, EXMC_SDNWE, EVENTOUT; additional ADC01_IN7.
33 PC4 bidirectional Default GPIO PC4, 5 V tolerant (5VT); alternates ENET_MII_RXD0, ENET_RMII_RXD0, EVENTOUT; additional ADC01_IN14.
34 PC5 bidirectional Default GPIO PC5, 5 V tolerant (5VT); alternates USART2_RX, ENET_MII_RXD1, ENET_RMII_RXD1, EVENTOUT; additional ADC01_IN15.
35 PB0 bidirectional Default GPIO PB0, 5 V tolerant (5VT); alternates TIMER0_CH1_ON, TIMER2_CH2, TIMER7_CH1_ON, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D1, ENET_MII_RXD2, SDIO_D1, EVENTOUT; additional ADC01_IN8 and IREF.
36 PB1 bidirectional Default GPIO PB1, 5 V tolerant (5VT); alternates TIMER0_CH2_ON, TIMER2_CH3, TIMER7_CH2_ON, USBHS_ULPI_D2, ENET_MII_RXD3, SDIO_D2, EVENTOUT; additional ADC01_IN9.
37 PB2 bidirectional Default GPIO PB2 (also BOOT1), 5 V tolerant (5VT); alternates TIMER1_CH3, SPI2_MOSI, I2S2_SD, USBHS_ULPI_D4, SDIO_CK, EVENTOUT.
38 PE7 bidirectional Default GPIO PE7, 5 V tolerant (5VT); alternates TIMER0_ETI, EXMC_D4, EVENTOUT.
39 PE8 bidirectional Default GPIO PE8, 5 V tolerant (5VT); alternates TIMER0_CH0_ON, EXMC_D5, EVENTOUT.
40 PE9 bidirectional Default GPIO PE9, 5 V tolerant (5VT); alternates TIMER0_CH0, EXMC_D6, EVENTOUT.
41 PE10 bidirectional Default GPIO PE10, 5 V tolerant (5VT); alternates TIMER0_CH1_ON, EXMC_D7, EVENTOUT.
42 PE11 bidirectional Default GPIO PE11, 5 V tolerant (5VT); alternates TIMER0_CH1, EXMC_D8, EVENTOUT.
43 PE12 bidirectional Default GPIO PE12, 5 V tolerant (5VT); alternates TIMER0_CH2_ON, EXMC_D9, EVENTOUT.
44 PE13 bidirectional Default GPIO PE13, 5 V tolerant (5VT); alternates TIMER0_CH2, EXMC_D10, EVENTOUT.
45 PE14 bidirectional Default GPIO PE14, 5 V tolerant (5VT); alternates TIMER0_CH3, EXMC_D11, EVENTOUT.
46 PE15 bidirectional Default GPIO PE15, 5 V tolerant (5VT); alternates TIMER0_BRKIN, EXMC_D12, EVENTOUT.
47 PB10 bidirectional Default GPIO PB10, 5 V tolerant (5VT); alternates TIMER1_CH2, I2C1_SCL, SPI1_SCK, I2S1_CK, I2S2_MCK, USART2_TX, USBHS_ULPI_D3, ENET_MII_RX_ER, SDIO_D7, EVENTOUT.
48 PB11 bidirectional Default GPIO PB11, 5 V tolerant (5VT); alternates TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX, USBHS_ULPI_D4, ENET_MII_TX_EN, ENET_RMII_TX_EN, EVENTOUT.
49 NC unconnected Not connected (NC) per the pin table.
50 VDD power_in Digital power supply pin (default function VDD).
51 PB12 bidirectional Default GPIO PB12, 5 V tolerant (5VT); alternates TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, I2S1_WS, USART2_CK, CAN1_RX, USBHS_ULPI_D5, ENET_MII_TXD0, ENET_RMII_TXD0, USBHS_ID, EVENTOUT.
52 PB13 bidirectional Default GPIO PB13, 5 V tolerant (5VT); alternates TIMER0_CH0_ON, SPI1_SCK, I2S1_CK, USART2_CTS, CAN1_TX, USBHS_ULPI_D6, ENET_MII_TXD1, ENET_RMII_TXD1, EVENTOUT, I2C1_TXFRAME; additional USBHS_VBUS.
53 PB14 bidirectional Default GPIO PB14, 5 V tolerant (5VT); alternates TIMER0_CH1_ON, TIMER7_CH1_ON, SPI1_MISO, I2S1_ADD_SD, USART2_RTS, TIMER11_CH0, USBHS_DM, EVENTOUT.
54 PB15 bidirectional Default GPIO PB15, 5 V tolerant (5VT); alternates RTC_REFIN, TIMER0_CH2_ON, TIMER7_CH2_ON, SPI1_MOSI, I2S1_SD, TIMER11_CH1, USBHS_DP, EVENTOUT.
55 PD8 bidirectional Default GPIO PD8, 5 V tolerant (5VT); alternates USART2_TX, EXMC_D13, EVENTOUT.
56 PD9 bidirectional Default GPIO PD9, 5 V tolerant (5VT); alternates USART2_RX, EXMC_D14, EVENTOUT.
57 PD10 bidirectional Default GPIO PD10, 5 V tolerant (5VT); alternates USART2_CK, EXMC_D15, EVENTOUT.
58 PD11 bidirectional Default GPIO PD11, 5 V tolerant (5VT); alternates USART2_CTS, EXMC_A16, EVENTOUT.
59 PD12 bidirectional Default GPIO PD12, 5 V tolerant (5VT); alternates TIMER3_CH0, USART2_RTS, EXMC_A17, EVENTOUT.
60 PD13 bidirectional Default GPIO PD13, 5 V tolerant (5VT); alternates TIMER3_CH1, EXMC_A18, EVENTOUT.
61 PD14 bidirectional Default GPIO PD14, 5 V tolerant (5VT); alternates TIMER3_CH2, EXMC_D0, EVENTOUT.
62 PD15 bidirectional Default GPIO PD15, 5 V tolerant (5VT); alternates TIMER3_CH3, EXMC_D1, EVENTOUT, CTC_SYNC.
63 PC6 bidirectional Default GPIO PC6, 5 V tolerant (5VT); alternates TIMER2_CH0, TIMER7_CH0, I2S1_MCK, USART5_TX, SDIO_D6, DCI_D0, EVENTOUT.
64 PC7 bidirectional Default GPIO PC7, 5 V tolerant (5VT); alternates TIMER2_CH1, TIMER7_CH1, SPI1_SCK, I2S1_CK, I2S2_MCK, USART5_RX, SDIO_D7, DCI_D1, EVENTOUT.
65 PC8 bidirectional Default GPIO PC8, 5 V tolerant (5VT); alternates TIMER2_CH2, TIMER7_CH2, USART5_CK, SDIO_D0, DCI_D2, EVENTOUT.
66 PC9 bidirectional Default GPIO PC9, 5 V tolerant (5VT); alternates CK_OUT1, TIMER2_CH3, TIMER7_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1, DCI_D3, EVENTOUT.
67 PA8 bidirectional Default GPIO PA8, 5 V tolerant (5VT); alternates CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF, SDIO_D1, EVENTOUT, CTC_SYNC.
68 PA9 bidirectional Default GPIO PA9, 5 V tolerant (5VT); alternates TIMER0_CH1, I2C2_SMBA, SPI1_SCK, I2S1_CK, USART0_TX, SDIO_D2, DCI_D0, EVENTOUT; additional USBFS_VBUS.
69 PA10 bidirectional Default GPIO PA10, 5 V tolerant (5VT); alternates TIMER0_CH2, USART0_RX, USBFS_ID, DCI_D1, EVENTOUT, I2C2_TXFRAME.
70 PA11 bidirectional Default GPIO PA11, 5 V tolerant (5VT); alternates TIMER0_CH3, USART0_CTS, USART5_TX, CAN0_RX, USBFS_DM, EVENTOUT.
71 PA12 bidirectional Default GPIO PA12, 5 V tolerant (5VT); alternates TIMER0_ETI, USART0_RTS, USART5_RX, CAN0_TX, USBFS_DP, EVENTOUT.
72 PA13 bidirectional Default JTMS/SWDIO, then PA13, 5 V tolerant (5VT); alternate EVENTOUT.
73 NC unconnected Not connected (NC) per the pin table.
74 VSS power_in Digital ground pin (default function VSS).
75 VDD power_in Digital power supply pin (default function VDD).
76 PA14 bidirectional Default JTCK/SWCLK, then PA14, 5 V tolerant (5VT); alternate EVENTOUT.
77 PA15 bidirectional Default JTDI, then PA15, 5 V tolerant (5VT); alternates TIMER1_CH0, TIMER1_ETI, SPI0_NSS, SPI2_NSS/I2S2_WS, USART0_TX, EVENTOUT.
78 PC10 bidirectional Default GPIO PC10, 5 V tolerant (5VT); alternates SPI2_SCK/I2S2_CK, USART2_TX, UART3_TX, SDIO_D2, DCI_D8, EVENTOUT.
79 PC11 bidirectional Default GPIO PC11, 5 V tolerant (5VT); alternates I2S2_ADD_SD, SPI2_MISO, USART2_RX, UART3_RX, SDIO_D3, DCI_D4, EVENTOUT.
80 PC12 bidirectional Default GPIO PC12, 5 V tolerant (5VT); alternates I2C1_SDA, SPI2_MOSI/I2S2_SD, USART2_CK, UART4_TX, SDIO_CK, DCI_D9, EVENTOUT.
81 PD0 bidirectional Default GPIO PD0, 5 V tolerant (5VT); alternates SPI2_MOSI/I2S2_SD, CAN0_RX, EXMC_D2, EVENTOUT.
82 PD1 bidirectional Default GPIO PD1, 5 V tolerant (5VT); alternates SPI1_NSS/I2S1_WS, CAN0_TX, EXMC_D3, EVENTOUT.
83 PD2 bidirectional Default GPIO PD2, 5 V tolerant (5VT); alternates TIMER2_ETI, UART4_RX, SDIO_CMD, DCI_D11, EVENTOUT.
84 PD3 bidirectional Default GPIO PD3, 5 V tolerant (5VT); alternates SPI1_SCK/I2S1_CK, USART1_CTS, EXMC_CLK, DCI_D5, EVENTOUT.
85 PD4 bidirectional Default GPIO PD4, 5 V tolerant (5VT); alternates USART1_RTS, EXMC_NOE, EVENTOUT.
86 PD5 bidirectional Default GPIO PD5, 5 V tolerant (5VT); alternates USART1_TX, EXMC_NWE, EVENTOUT.
87 PD6 bidirectional Default GPIO PD6, 5 V tolerant (5VT); alternates SPI2_MOSI/I2S2_SD, USART1_RX, EXMC_NWAIT, DCI_D10, EVENTOUT.
88 PD7 bidirectional Default GPIO PD7, 5 V tolerant (5VT); alternates USART1_CK, EXMC_NE0/EXMC_NCE1, EVENTOUT.
89 PB3 bidirectional Default JTDO/PB3, 5 V tolerant (5VT); alternates TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK/I2S2_CK, USART0_RX, I2C1_SDA, EVENTOUT.
90 PB4 bidirectional Default NJTRST/PB4, 5 V tolerant (5VT); alternates TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2S2_ADD_SD, I2C2_SDA, SDIO_D0, EVENTOUT, I2C0_TXFRAME.
91 PB5 bidirectional Default GPIO PB5, 5 V tolerant (5VT); alternates TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI/I2S2_SD, CAN1_RX, USBHS_ULPI_D7, ENET_PPS_OUT, DCI_D10, EVENTOUT.
92 PB6 bidirectional Default GPIO PB6, 5 V tolerant (5VT); alternates TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX, DCI_D5, EVENTOUT.
93 PB7 bidirectional Default GPIO PB7, 5 V tolerant (5VT); alternates TIMER3_CH1, I2C0_SDA, USART0_RX, EXMC_NL, DCI_VSYNC, EVENTOUT.
94 BOOT0 bidirectional Default BOOT0 pin, 5 V tolerant (5VT), used for boot-mode selection (see section 3.4).
95 PB8 bidirectional Default GPIO PB8, 5 V tolerant (5VT); alternates TIMER1_CH0, TIMER1_ETI, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX, ENET_MII_TXD3, SDIO_D4, DCI_D6, EVENTOUT.
96 PB9 bidirectional Default GPIO PB9, 5 V tolerant (5VT); alternates TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS/I2S1_WS, CAN0_TX, SDIO_D5, DCI_D7, EVENTOUT.
97 PE0 bidirectional Default GPIO PE0, 5 V tolerant (5VT); alternates TIMER3_ETI, EXMC_NBL0, DCI_D2, EVENTOUT.
98 PE1 bidirectional Default GPIO PE1, 5 V tolerant (5VT); alternates TIMER0_CH1_ON, EXMC_NBL1, DCI_D3, EVENTOUT.
99 VSS power_in Digital ground pin (default function VSS).
100 VDD power_in Digital power supply pin (default function VDD).

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
External voltage range VDD -0.3 3.6 V Referenced to VSS (printed VSS - 0.3 / VSS + 3.6) 80
External analog supply voltage VDDA -0.3 3.6 V Referenced to VSSA (printed VSSA - 0.3 / VSSA + 3.6) 80
External battery supply voltage VBAT -0.3 3.6 V Referenced to VSS (printed VSS - 0.3 / VSS + 3.6) 80
Input voltage on other I/O VIN -0.3 3.6 V 80
Input voltage on 5V tolerant pin VIN -0.3 V Printed max VDD + 3.6 V; VIN max not to exceed 5.5 V (footnote 3) 80
Variations between different VDD power pins /ΔVDDX/ 50 mV 80
Variations between different ground pins /VSSX −VSS/ 50 mV 80
Maximum current for GPIO pins IIO 25 mA 80
Operating temperature range TA -40 85 °C 80
Power dissipation (LQFP100) PD 697 mW TA = 85°C, LQFP100 80
Storage temperature range TSTG -65 150 °C 80
Maximum junction temperature TJ 125 °C 80
Supply voltage VDD 2.6 3.3 3.6 V 80
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 80
Battery supply voltage VBAT 1.8 3.6 V 80
AHB clock frequency fHCLK 200 MHz 81
APB1 clock frequency fAPB1 50 MHz 81
APB2 clock frequency fAPB2 100 MHz 81
VDD rise time rate tVDD 0 μs/ V Printed max is infinity (no limit) 81
VDD fall time rate 20 μs/ V Printed max is infinity (no limit) 81
Electrostatic discharge voltage (human body model) VESD(HBM) 2000 V TA=25 °C; JS-001-2017 90
Electrostatic discharge voltage (charge device model) VESD(CDM) 500 V TA=25 °C; JS-002-2018 90
Static latch-up I-test LU -200 200 mA TA=105 °C; JESD78 90
Static latch-up Vsupply over voltage 5.4 V 90
Crystal or ceramic frequency (HXTAL) fHXTAL 4 25 32 MHz 2.6 V ≤ VDD ≤ 3.6 V 91
Crystal or ceramic duty cycle (HXTAL) Ducy(HXTAL) 30 50 70 % 91
External clock source or oscillator frequency (HXTAL bypass) fHXTAL_ext 1 50 MHz 2.6 V ≤ VDD ≤ 3.6 V 91
OSCIN high or low time (HXTAL bypass) tH/L(HXTAL) 5 ns 91
OSCIN rise or fall time (HXTAL bypass) tR/F(HXTAL) 10 ns 91
Duty cycle (HXTAL bypass) Ducy(HXTAL) 40 60 % 91
Crystal or ceramic duty cycle (LXTAL) Ducy(LXTAL) 30 70 % 92
External clock source or oscillator frequency (LXTAL bypass) fLXTAL_ext 32.768 1000 kHz VDD = 3.3 V 92
OSC32IN high or low time (LXTAL bypass) tH/L(LXTAL) 450 ns 92
OSC32IN rise or fall time (LXTAL bypass) tR/F(LXTAL) 50 ns 92
Duty cycle (LXTAL bypass) Ducy(LXTAL) 30 50 70 % 92
IRC16M oscillator frequency accuracy, factory-trimmed ACCIRC16M -1 1 % VDD = VDDA = 3.3 V, TA = 25 °C 93
IRC16M oscillator frequency accuracy, factory-trimmed ACCIRC16M -1.73 1.1 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 93
IRC16M oscillator duty cycle DucyIRC16M 45 50 55 % VDD = VDDA = 3.3 V 93
IRC48M oscillator frequency accuracy, factory-trimmed ACCIRC48M -2 2 % VDD = VDDA = 3.3 V, TA = 25 °C 93
IRC48M oscillator frequency accuracy, factory-trimmed ACCIRC48M -1.31 0.39 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 93
IRC48M oscillator duty cycle DucyIRC48M 45 50 55 % VDD = VDDA = 3.3 V 93
PLL input clock frequency fPLLIN 1 4 MHz 94
PLL output clock frequency fPLLOUT 100 500 MHz 94
PLL VCO output clock frequency fVCO 32 344 MHz 94
PLL lock time tLOCK 400 μs 94
Number of guaranteed program/erase cycles before failure (Endurance) PECYC 100 kcycles TA = -40 °C ~ +85 °C 96
Word programming time tPROG 37.5 180 μs TA = -40°C ~ +85 °C 96
Sector (16kB) erase time tERASE16kB 200 2000 ms TA = -40°C ~ +85 °C 96
Sector (64kB) erase time tERASE64kB 300 4000 ms 96
Sector (128kB) erase time tERASE128kB 600 8000 ms 96
Mass erase time (512K) tMERASE(512K) 2.4 32 s TA = -40°C ~ +85 °C 96
Low level output voltage for an IO Pin (IO_Speed level 3) VOL 0.1 V IO_Speed:level 3, IIO = +8 mA, VDD = 3.3 V 98
High level output voltage for an IO Pin (IO_Speed level 3) VOH 3.18 V IO_Speed:level 3, IIO = +8 mA, VDD = 3.3 V 98
Low level output voltage for an IO Pin (IO_Speed level 0) VOL 0.63 V IO_Speed:level 0, IIO = +4 mA, VDD = 3.3 V 99
High level output voltage for an IO Pin (IO_Speed level 0) VOH 2.48 V IO_Speed:level 0, IIO = +4 mA, VDD = 3.3 V 99
NRST Input low level voltage VIL(NRST) -0.3 V VDD = VDDA = 3.3 V; printed max 0.3 VDD (not numeric) 96
ADC operating clock fADC 0.1 40 MHz 100
Thermal resistance, junction to cold plate (LQFP100) θJC 31.68 °C/W Cold plate, 2S2P PCB 128
Thermal characterization parameter, junction to board (LQFP100) ψJB 13.85 °C/W Natural convection, 2S2P PCB 128

CAD (KiCad official)

  • Symbol: GD32F427VET6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: gd32f427vet6-etched.step / gd32f427vet6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f427vet6.step / gd32f427vet6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (131 pp, sha256 7b84a91279c53e4c, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF