# GD32F427RET6

**GigaDevice Semicon Beijing** · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)

GD32F427RET6 from GigaDevice Semicon Beijing, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Default function VBAT, the backup-domain supply pin shown as VBAT-powered in the block diagram. |
| 2 | PC13-TAMPER-RTC | bidirectional | Default PC13, 5 V tolerant I/O, with additional functions RTC_TAMP0, RTC_OUT and RTC_TS. |
| 3 | PC14-OSC32IN | bidirectional | Default PC14, 5 V tolerant I/O, with additional function OSC32IN. |
| 4 | PC15-OSC32OUT | bidirectional | Default PC15, 5 V tolerant I/O, with additional function OSC32OUT. |
| 5 | PH0-OSCIN | bidirectional | Default PH0, 5 V tolerant I/O, with additional function OSCIN. |
| 6 | PH1-OSCOUT | bidirectional | Default PH1, 5 V tolerant I/O, with additional function OSCOUT. |
| 7 | NRST | input | Default function NRST, the reset pin whose characteristics are given in section 4.11. |
| 8 | PC0 | bidirectional | Default PC0, 5 V tolerant I/O, with alternate USBHS_ULPI_STP and EXMC_SDNWE, and additional ADC012_IN10. |
| 9 | PC1 | bidirectional | Default PC1, 5 V tolerant I/O, with alternate SPI2_MOSI, I2S2_SD, SPI1_MOSI, I2S1_SD and ENET_MDC, and additional ADC012_IN11. |
| 10 | PC2 | bidirectional | Default PC2, 5 V tolerant I/O, with alternate SPI1_MISO, I2S1_ADD_SD, USBHS_ULPI_DIR and ENET_MII_TXD2, and additional ADC012_IN12. |
| 11 | PC3 | bidirectional | Default PC3, 5 V tolerant I/O, with alternate SPI1_MOSI, I2S1_SD, USBHS_ULPI_NXT and ENET_MII_TX_CLK, and additional ADC012_IN13. |
| 12 | VSSA | power_in | Default function VSSA, the analog supply ground pin. |
| 13 | VDDA | power_in | Default function VDDA, the analog supply pin. |
| 14 | PA0-WKUP | bidirectional | Default PA0, 5 V tolerant I/O, with alternate TIMER1_CH0, USART1_CTS and ENET_MII_CRS, and additional ADC012_IN0 and WKUP. |
| 15 | PA1 | bidirectional | Default PA1, 5 V tolerant I/O, with alternate TIMER1_CH1, USART1_RTS and ENET_RMII_REF_CLK, and additional ADC012_IN1. |
| 16 | PA2 | bidirectional | Default PA2, 5 V tolerant I/O, with alternate TIMER1_CH2, I2S_CKIN, USART1_TX and ENET_MDIO, and additional ADC012_IN2. |
| 17 | PA3 | bidirectional | Default PA3, 5 V tolerant I/O, with alternate TIMER1_CH3, I2S1_MCK, USART1_RX and USBHS_ULPI_D0, and additional ADC012_IN3. |
| 18 | VSS | power_in | Default function VSS, the ground pin. |
| 19 | VDD | power_in | Default function VDD, the digital supply pin. |
| 20 | PA4 | bidirectional | Default PA4, with alternate SPI0_NSS, SPI2_NSS/I2S2_WS, USART1_CK, USBHS_SOF and DCI_HSYNC, and additional ADC01_IN4 and DAC_OUT0. |
| 21 | PA5 | bidirectional | Default PA5, with alternate TIMER1_CH0, SPI0_SCK and USBHS_ULPI_CK, and additional ADC01_IN5 and DAC_OUT1. |
| 22 | PA6 | bidirectional | Default PA6, 5 V tolerant I/O, with alternate TIMER0_BRKIN, SPI0_MISO, SDIO_CMD and DCI_PIXCLK, and additional ADC01_IN6. |
| 23 | PA7 | bidirectional | Default PA7, 5 V tolerant I/O, with alternate TIMER0_CH0_ON, SPI0_MOSI, ENET_MII_RX_DV and EXMC_SDNWE, and additional ADC01_IN7. |
| 24 | PC4 | bidirectional | Default PC4, 5 V tolerant I/O, with alternate ENET_MII_RXD0 and ENET_RMII_RXD0, and additional ADC01_IN14. |
| 25 | PC5 | bidirectional | Default PC5, 5 V tolerant I/O, with alternate USART2_RX, ENET_MII_RXD1 and ENET_RMII_RXD1, and additional ADC01_IN15. |
| 26 | PB0 | bidirectional | Default PB0, 5 V tolerant I/O, with alternate TIMER0_CH1_ON, SPI2_MOSI, USBHS_ULPI_D1 and SDIO_D1, and additional ADC01_IN8 and IREF. |
| 27 | PB1 | bidirectional | Default PB1, 5 V tolerant I/O, with alternate TIMER0_CH2_ON, USBHS_ULPI_D2, ENET_MII_RXD3 and SDIO_D2, and additional ADC01_IN9. |
| 28 | PB2 | bidirectional | Default PB2 with BOOT1, 5 V tolerant I/O, with alternate TIMER1_CH3, SPI2_MOSI, USBHS_ULPI_D4 and SDIO_CK. |
| 29 | PB10 | bidirectional | Default PB10, 5 V tolerant I/O, with alternate TIMER1_CH2, I2C1_SCL, SPI1_SCK, USART2_TX, ENET_MII_RX_ER and SDIO_D7. |
| 30 | PB11 | bidirectional | Default PB11, 5 V tolerant I/O, with alternate TIMER1_CH3, I2C1_SDA, I2S_CKIN, USART2_RX and ENET_MII_TX_EN. |
| 31 | NC | unconnected | Not connected, as marked NC in the LQFP64 pin definition table. |
| 32 | VDD | power_in | Default function VDD, the digital supply pin. |
| 33 | PB12 | bidirectional | Default PB12, 5 V tolerant I/O, with alternate TIMER0_BRKIN, I2C1_SMBA, SPI1_NSS, CAN1_RX and USBHS_ID. |
| 34 | PB13 | bidirectional | Default PB13, 5 V tolerant I/O, with alternate TIMER0_CH0_ON, SPI1_SCK, CAN1_TX and ENET_MII_TXD1, and additional USBHS_VBUS. |
| 35 | PB14 | bidirectional | Default PB14, 5 V tolerant I/O, with alternate TIMER0_CH1_ON, SPI1_MISO, USART2_RTS, TIMER11_CH0 and USBHS_DM. |
| 36 | PB15 | bidirectional | Default PB15, 5 V tolerant I/O, with alternate RTC_REFIN, TIMER0_CH2_ON, SPI1_MOSI, TIMER11_CH1 and USBHS_DP. |
| 37 | PC6 | bidirectional | Default PC6, 5 V tolerant I/O, with alternate TIMER2_CH0, I2S1_MCK, USART5_TX, SDIO_D6 and DCI_D0. |
| 38 | PC7 | bidirectional | Default PC7, 5 V tolerant I/O, with alternate TIMER2_CH1, SPI1_SCK, I2S1_CK, USART5_RX, SDIO_D7 and DCI_D1. |
| 39 | PC8 | bidirectional | Default PC8, 5 V tolerant I/O, with alternate TIMER2_CH2, USART5_CK, SDIO_D0 and DCI_D2. |
| 40 | PC9 | bidirectional | Default PC9, 5 V tolerant I/O, with alternate CK_OUT1, TIMER2_CH3, I2C2_SDA, I2S_CKIN, SDIO_D1 and DCI_D3. |
| 41 | PA8 | bidirectional | Default PA8, 5 V tolerant I/O, with alternate CK_OUT0, TIMER0_CH0, I2C2_SCL, USART0_CK, USBFS_SOF and CTC_SYNC. |
| 42 | PA9 | bidirectional | Default PA9, 5 V tolerant I/O, with alternate TIMER0_CH1, I2C2_SMBA, SPI1_SCK, USART0_TX and DCI_D0, and additional USBFS_VBUS. |
| 43 | PA10 | bidirectional | Default PA10, 5 V tolerant I/O, with alternate TIMER0_CH2, USART0_RX, USBFS_ID and DCI_D1. |
| 44 | PA11 | bidirectional | Default PA11, 5 V tolerant I/O, with alternate TIMER0_CH3, USART0_CTS, USART5_TX, CAN0_RX and USBFS_DM. |
| 45 | PA12 | bidirectional | Default PA12, 5 V tolerant I/O, with alternate TIMER0_ETI, USART0_RTS, USART5_RX, CAN0_TX and USBFS_DP. |
| 46 | PA13 | bidirectional | Default JTMS, SWDIO, PA13, 5 V tolerant I/O with alternate function EVENTOUT. |
| 47 | NC | unconnected | Not connected, as marked NC in the LQFP64 pin definition table. |
| 48 | VDD | power_in | Default function VDD, the digital supply pin. |
| 49 | PA14 | bidirectional | Default JTCK, SWCLK, PA14, 5 V tolerant I/O with alternate function EVENTOUT. |
| 50 | PA15 | bidirectional | Default JTDI, PA15, 5 V tolerant I/O, with alternate TIMER1_CH0, SPI0_NSS, SPI2_NSS/I2S2_WS and USART0_TX. |
| 51 | PC10 | bidirectional | Default PC10, 5 V tolerant I/O, with alternate SPI2_SCK, USART2_TX, UART3_TX and SDIO_D2. |
| 52 | PC11 | bidirectional | Default PC11, 5 V tolerant I/O, with alternate SPI2_MISO, USART2_RX, UART3_RX and SDIO_D3. |
| 53 | PC12 | bidirectional | Default PC12, 5 V tolerant I/O, with alternate I2C1_SDA, SPI2_MOSI, USART2_CK, UART4_TX and SDIO_CK. |
| 54 | PD2 | bidirectional | Default PD2, 5 V tolerant I/O, with alternate TIMER2_ETI, UART4_RX, SDIO_CMD and DCI_D11. |
| 55 | PB3 | bidirectional | Default JTDO, PB3, 5 V tolerant I/O, with alternate TRACESWO, TIMER1_CH1, SPI0_SCK, SPI2_SCK, USART0_RX and I2C1_SDA. |
| 56 | PB4 | bidirectional | Default NJTRST, PB4, 5 V tolerant I/O, with alternate TIMER2_CH0, SPI0_MISO, SPI2_MISO, I2C2_SDA and SDIO_D0. |
| 57 | PB5 | bidirectional | Default PB5, 5 V tolerant I/O, with alternate TIMER2_CH1, I2C0_SMBA, SPI0_MOSI, SPI2_MOSI, CAN1_RX and USBHS_ULPI_D7. |
| 58 | PB6 | bidirectional | Default PB6, 5 V tolerant I/O, with alternate TIMER3_CH0, I2C0_SCL, USART0_TX, CAN1_TX and DCI_D5. |
| 59 | PB7 | bidirectional | Default PB7, 5 V tolerant I/O, with alternate TIMER3_CH1, I2C0_SDA, USART0_RX and DCI_VSYNC. |
| 60 | BOOT0 | bidirectional | Default function BOOT0, 5 V tolerant I/O pin. |
| 61 | PB8 | bidirectional | Default PB8, 5 V tolerant I/O, with alternate TIMER1_CH0, TIMER3_CH2, TIMER9_CH0, I2C0_SCL, CAN0_RX and SDIO_D4. |
| 62 | PB9 | bidirectional | Default PB9, 5 V tolerant I/O, with alternate TIMER1_CH1, TIMER3_CH3, TIMER10_CH0, I2C0_SDA, SPI1_NSS, CAN0_TX and SDIO_D5. |
| 63 | VSS | power_in | Default function VSS, the ground pin. |
| 64 | VDD | power_in | Default function VDD, the digital supply pin. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V |  | 81 |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 81 |
| Battery supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 81 |
| AHB clock frequency | fHCLK |  |  | 200 | MHz |  | 81 |
| ADC clock | fADC | 0.1 |  | 40 | MHz |  | 100 |
| Crystal or ceramic frequency | fHXTAL | 4 | 25 | 32 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 91 |
| IRC16M frequency accuracy, factory-trimmed | ACCIRC16M | -1 |  | 1 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 93 |
| IRC16M frequency accuracy, factory-trimmed | ACCIRC16M | -1.73 |  | 1.1 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 93 |
| IRC48M frequency accuracy, factory-trimmed | ACCIRC48M | -2 |  | 2 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 93 |
| IRC48M frequency accuracy, factory-trimmed | ACCIRC48M | -1.31 |  | 0.39 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 93 |
| PLL input clock frequency | fPLLIN | 1 |  | 4 | MHz |  | 94 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 80 |
| Storage temperature range | TSTG | -65 |  | 150 | °C |  | 80 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 80 |
| Maximum current for GPIO pins | IIO |  |  | 25 | mA |  | 80 |
| Power dissipation | PD |  |  | 772 | mW | Power dissipation at TA = 85°C of LQFP64 | 80 |
| Number of guaranteed program/erase cycles (Endurance) | PECYC | 50 |  |  | kcycles | TA = -40 °C ~ +85 °C | 96 |

## CAD (KiCad official)

- Symbol: `GD32F427RET6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `gd32f427ret6-etched.step` / `gd32f427ret6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32f427ret6.step` / `gd32f427ret6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](docs/gd32f427ret6-datasheet.pdf) (131 pp, sha256 `83e96a7176db4826`, retrieved 2026-10-27, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32f427ret6-datasheet.pdf)