component

GD32F350K8U6

Public Made by Adom

by adom

GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersgd32f350k8u6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
gd32f350k8u6 / README.md
History Download
Ray Publish 0.1.0 d8d6452 8d ago

GD32F350K8U6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)

GD32F350K8U6 from GigaDevice Semicon Beijing, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Digital power supply pin (default function VDD); the provided text gives no voltage limits for this pin.
2 PF0-OSCIN bidirectional 5 V tolerant GPIO PF0 with alternate CTC_SYNC and additional function OSCIN (external oscillator input).
3 PF1-OSCOUT bidirectional 5 V tolerant GPIO PF1 with additional function OSCOUT (external oscillator output).
4 NRST bidirectional Reset pin, default function NRST; the datasheet lists its I/O type as I/O.
5 VDDA power_in Analog power supply pin (default function VDDA); the provided text gives no voltage limits for this pin.
6 PA0-WKUP bidirectional Standard (non-5 V tolerant) GPIO PA0 with wake-up function WKUP0; alternates USART1_CTS, TIMER1_CH0, TIMER1_ETI, CMP0_OUT, TSI_G0_IO0, I2C1_SCL; additional ADC_IN0, CMP0_IM6, RTC_TAMP1.
7 PA1 bidirectional Standard (non-5 V tolerant) GPIO PA1; alternates USART1_RTS, TIMER1_CH1, TSI_G0_IO1, I2C1_SDA, EVENTOUT; additional ADC_IN1 and CMP0_IP.
8 PA2 bidirectional Standard (non-5 V tolerant) GPIO PA2; alternates USART1_TX, TIMER1_CH2, TIMER14_CH0, CMP1_OUT, TSI_G0_IO2; additional ADC_IN2 and CMP1_IM6.
9 PA3 bidirectional Standard (non-5 V tolerant) GPIO PA3; alternates USART1_RX, TIMER1_CH3, TIMER14_CH1, TSI_G0_IO3; additional ADC_IN3 and CMP1_IP.
10 PA4 bidirectional Standard (non-5 V tolerant) GPIO PA4; alternates SPI0_NSS/I2S0_WS, USART1_CK, TIMER13_CH0, TSI_G1_IO0, SPI1_NSS; additional ADC_IN4, CMP0_IM4, CMP1_IM4 and DAC0_OUT.
11 PA5 bidirectional Standard (non-5 V tolerant) GPIO PA5; alternates SPI0_SCK/I2S0_CK, CEC, TIMER1_CH0, TIMER1_ETI, TSI_G1_IO1; additional ADC_IN5, CMP0_IM5 and CMP1_IM5.
12 PA6 bidirectional Standard (non-5 V tolerant) GPIO PA6; alternates SPI0_MISO/I2S0_MCK, TIMER2_CH0, TIMER0_BKIN, TIMER15_CH0, CMP0_OUT, TSI_G1_IO2, EVENTOUT; additional ADC_IN6.
13 PA7 bidirectional Standard (non-5 V tolerant) GPIO PA7; alternates SPI0_MOSI/I2S0_SD, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0, CMP1_OUT, TSI_G1_IO3, EVENTOUT; additional ADC_IN7.
14 PB0 bidirectional Standard (non-5 V tolerant) GPIO PB0; alternates TIMER2_CH2, TIMER0_CH1_ON, TSI_G2_IO1, USART1_RX, EVENTOUT; additional ADC_IN8.
15 PB1 bidirectional Standard (non-5 V tolerant) GPIO PB1; alternates TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON, TSI_G2_IO2, SPI1_SCK; additional ADC_IN9.
16 PB2 bidirectional 5 V tolerant GPIO PB2 with alternate function TSI_G2_IO3.
17 VDD power_in Digital power supply pin (default function VDD); the provided text gives no voltage limits for this pin.
18 PA8 bidirectional 5 V tolerant GPIO PA8; alternates USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX, EVENTOUT, USBFS_SOF and CTC_SYNC.
19 PA9 bidirectional 5 V tolerant GPIO PA9; alternates USART0_TX, TIMER0_CH1, TIMER14_BKIN, TSI_G3_IO0, I2C0_SCL and USBFS_VBUS.
20 PA10 bidirectional 5 V tolerant GPIO PA10; alternates USART0_RX, TIMER0_CH2, TIMER16_BKIN, TSI_G3_IO1, I2C0_SDA and USBFS_ID.
21 PA11 bidirectional 5 V tolerant GPIO PA11; alternates USART0_CTS, TIMER0_CH3, CMP0_OUT, TSI_G3_IO2, EVENTOUT and SPI1_IO2; additional function USBFS_DM.
22 PA12 bidirectional 5 V tolerant GPIO PA12; alternates USART0_RTS, TIMER0_ETI, CMP1_OUT, TSI_G3_IO3, EVENTOUT and SPI1_IO3; additional function USBFS_DP.
23 PA13 bidirectional 5 V tolerant GPIO PA13; alternates IFRP_OUT, SWDIO and SPI1_MISO.
24 PA14 bidirectional 5 V tolerant GPIO PA14; alternates USART1_TX, SWCLK and SPI1_MOSI.
25 PA15 bidirectional 5 V tolerant GPIO PA15; alternates SPI0_NSS/I2S0_WS, USART1_RX, TIMER1_CH0, TIMER1_ETI, SPI1_NSS and EVENTOUT.
26 PB3 bidirectional 5 V tolerant GPIO PB3; alternates SPI0_SCK/I2S0_CK, TIMER1_CH1, TSI_G4_IO0 and EVENTOUT.
27 PB4 bidirectional 5 V tolerant GPIO PB4; alternates SPI0_MISO/I2S0_MCK, TIMER2_CH0, TSI_G4_IO1 and EVENTOUT.
28 PB5 bidirectional 5 V tolerant GPIO PB5 with wake-up function WKUP5; alternates SPI0_MOSI/I2S0_SD, I2C0_SMBA, TIMER15_BKIN and TIMER2_CH1.
29 PB6 bidirectional 5 V tolerant GPIO PB6; alternates I2C0_SCL, USART0_TX, TIMER15_CH0_ON and TSI_G4_IO2.
30 PB7 bidirectional 5 V tolerant GPIO PB7; alternates I2C0_SDA, USART0_RX, TIMER16_CH0_ON and TSI_G4_IO3.
31 BOOT0 input Boot pin, default function BOOT0, which selects the boot mode (see section 3.4 Boot modes).
32 PB8 bidirectional 5 V tolerant GPIO PB8; alternates I2C0_SCL, CEC, TIMER15_CH0 and TSITG.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Absolute maximum VDD external voltage range (min offset from VSS; max offset from VSS) VDD -0.3 3.6 V 44
Absolute maximum external analog supply voltage (min offset from VSSA; max offset from VSSA) VDDA -0.3 3.6 V 44
Absolute maximum external battery supply voltage (min offset from VSS; max offset from VSS) VBAT -0.3 3.6 V 44
Input voltage on 5V tolerant pin (max printed as VDD + 3.6 V, given as offset) VIN -0.3 3.6 V 5V tolerant pin; VIN maximum value cannot exceed 6.5 V 44
Input voltage on other I/O VIN -0.3 3.6 V 44
Variations between different VDD power pins /ΔVDDx/ 50 mV 44
Variations between different ground pins /VSSX −VSS/ 50 mV 44
Maximum current for GPIO pin IIO -25 25 mA 44
Operating temperature range TA -40 85 °C 44
Storage temperature range TSTG -55 150 °C 44
Maximum junction temperature TJ 125 °C 44
Supply voltage VDD 2.6 3.3 3.6 V 44
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 44
Battery supply voltage VBAT 1.8 3.6 V 44
AHB1 clock frequency fHCLK1 0 108 MHz 45
APB1 clock frequency fAPB1 0 54 MHz 45
VDD rise time rate (max printed as ∞) tVDD 0 μs /V 45
VDD fall time rate (max printed as ∞) tVDD 20 μs /V 45
NRST Input low level voltage (min -0.5 V; max printed as 0.3 VDD) VIL(NRST) -0.5 0.3 V / ×VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 59
NRST Input high level voltage (min printed as 0.7 VDD; max printed as VDD + 0.5) VIH(NRST) 0.7 0.5 ×VDD / V 59
Standard IO Low level input voltage (max printed as 0.3 VDD) VIL 0.3 ×VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 61
5V-tolerant IO Low level input voltage (max printed as 0.3 VDD) VIL 0.3 ×VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 61
Standard IO High level input voltage (min printed as 0.7 VDD) VIH 0.7 ×VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 61
5V-tolerant IO High level input voltage (min printed as 0.7 VDD) VIH 0.7 ×VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V 61
Low level output voltage for 8 IO Pins VOL 0.21 V VDD = 2.6 V, each IIO = +8 mA 61
Low level output voltage for 8 IO Pins VOL 0.19 V VDD = 3.3 V, each IIO = +8 mA 61
Low level output voltage for 8 IO Pins VOL 0.18 V VDD = 3.6 V, each IIO = +8 mA 61
High level output voltage for 8 IO Pins VOH 2.4 V VDD = 2.6 V, each IIO = +8 mA 61
High level output voltage for 8 IO Pins VOH 3.1 V VDD = 3.3 V, each IIO = +8 mA 61
High level output voltage for 8 IO Pins VOH 3.4 V VDD = 3.6 V, each IIO = +8 mA 61
Internal pull-up resistor RPU 30 40 50 kΩ All pins VIN = VSS 61
Internal pull-up resistor RPU 7.5 10 13.5 kΩ PA10 61
Internal pull-down resistor RPD 30 40 50 kΩ All pins VIN = VDD 61
Internal pull-down resistor RPD 7.5 10 13.5 kΩ PA10 61
Crystal or ceramic frequency fHXTAL 4 8 32 MHz 2.6 V ≤ VDD ≤ 3.6 V 55
IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M -4 5 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 57
IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M -2 2 % VDD = VDDA = 3.3 V, TA = 0°C ~ +85°C 57
IRC8M oscillator Frequency accuracy, Factory-trimmed ACCIRC8M -1 1 % VDD = VDDA = 3.3 V, TA = 25°C 57
Low Speed Internal oscillator (IRC40K) frequency fIRC40K 20 40 45 kHz VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 57
PLL input clock frequency fPLLIN 1 25 MHz 58
PLL output clock frequency fPLLOUT 16 108 MHz 58
ADC clock fADC 0.1 40 MHz 62
Number of guaranteed program /erase cycles before failure (Endurance) PECYC 100 kcycles 59
Word programming time wtPROG 86 μs TA = -40 °C ~ +85 °C 59
Low Voltage Detector Threshold VLVD 3.03 3.11 3.19 V LVDT[2:0] = 000, rising edge 54
Low Voltage Detector Threshold VLVD 2.94 3.01 3.07 V LVDT[2:0] = 000, falling edge 54
Low Voltage Detector Threshold VLVD 2.9 2.97 3.04 V LVDT[2:0] = 001, rising edge 54
Low Voltage Detector Threshold VLVD 2.8 2.87 2.93 V LVDT[2:0] = 001, falling edge 54
Low Voltage Detector Threshold VLVD 2.76 2.83 2.9 V LVDT[2:0] = 010, rising edge 54
Low Voltage Detector Threshold VLVD 2.66 2.73 2.79 V LVDT[2:0] = 010, falling edge 54
Low Voltage Detector Threshold VLVD 2.63 2.69 2.76 V LVDT[2:0] = 011, rising edge 54
Low Voltage Detector Threshold VLVD 2.53 2.59 2.66 V LVDT[2:0] = 011, falling edge 54
Low Voltage Detector Threshold VLVD 2.49 2.55 2.62 V LVDT[2:0] = 100, rising edge 54
Low Voltage Detector Threshold VLVD 2.39 2.45 2.52 V LVDT[2:0] = 100, falling edge 54
Low Voltage Detector Threshold VLVD 2.36 2.42 2.47 V LVDT[2:0] = 101, rising edge 54
Low Voltage Detector Threshold VLVD 2.26 2.32 2.37 V LVDT[2:0] = 101, falling edge 54
Low Voltage Detector Threshold VLVD 2.22 2.28 2.33 V LVDT[2:0] = 110, rising edge 54
Low Voltage Detector Threshold VLVD 2.13 2.17 2.22 V LVDT[2:0] = 110, falling edge 54
Low Voltage Detector Threshold VLVD 2.08 2.14 2.19 V LVDT[2:0] = 111, rising edge 54
Low Voltage Detector Threshold VLVD 1.99 2.03 2.08 V LVDT[2:0] = 111, falling edge 54

CAD (KiCad official)

  • Symbol: GD32F350K8U6
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: gd32f350k8u6-etched.step / gd32f350k8u6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f350k8u6.step / gd32f350k8u6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (77 pp, sha256 5ff2eb8e6cbd736d, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF