# GD32F305VGT6

**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F305VGT6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant I/O; default function PE2, alternate functions TRACECK and EXMC_A23. |
| 2 | PE3 | bidirectional | 5 V tolerant I/O; default function PE3, alternate functions TRACED0 and EXMC_A19. |
| 3 | PE4 | bidirectional | 5 V tolerant I/O; default function PE4, alternate functions TRACED1 and EXMC_A20. |
| 4 | PE5 | bidirectional | 5 V tolerant I/O; default function PE5, alternate functions TRACED2 and EXMC_A21; remap TIMER8_CH0 (footnote 3, VG devices). |
| 5 | PE6 | bidirectional | 5 V tolerant I/O; default function PE6, alternate functions TRACED3 and EXMC_A22; remap TIMER8_CH1 (footnote 3, VG devices). |
| 6 | VBAT | power_in | Default function VBAT; the pin table gives no voltage limits for this pin. |
| 7 | PC13-TAMPER-RTC | bidirectional | I/O; default function PC13, alternate function TAMPER-RTC. |
| 8 | PC14-OSC32IN | bidirectional | I/O; default function PC14, alternate function OSC32IN. |
| 9 | PC15-OSC32OUT | bidirectional | I/O; default function PC15, alternate function OSC32OUT. |
| 10 | VSS_5 | power_in | Digital ground pin, default function VSS_5. |
| 11 | VDD_5 | power_in | Digital supply pin, default function VDD_5. |
| 12 | OSCIN | input | External oscillator input; default function OSCIN, remappable to PD0. |
| 13 | OSCOUT | output | External oscillator output; default function OSCOUT, remappable to PD1. |
| 14 | NRST | bidirectional | Reset pin with default function NRST; the pin table gives no further limits. |
| 15 | PC0 | bidirectional | I/O; default function PC0, alternate function ADC01_IN10. |
| 16 | PC1 | bidirectional | I/O; default function PC1, alternate function ADC01_IN11. |
| 17 | PC2 | bidirectional | I/O; default function PC2, alternate function ADC01_IN12. |
| 18 | PC3 | bidirectional | I/O; default function PC3, alternate function ADC01_IN13. |
| 19 | VSSA | power_in | Analog ground pin, default function VSSA. |
| 20 | VREF- | power_in | Default function VREF-; the pin table gives no further limits. |
| 21 | VREF+ | power_in | Default function VREF+; the pin table gives no further limits. |
| 22 | VDDA | power_in | Analog supply pin, default function VDDA. |
| 23 | PA0-WKUP | bidirectional | I/O; default function PA0, alternate functions WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0 and TIMER7_ETI (TIMER7_ETI per footnote 4, VE/G devices). |
| 24 | PA1 | bidirectional | I/O; default function PA1, alternate functions USART1_RTS, ADC01_IN1, TIMER1_CH1 and TIMER4_CH1. |
| 25 | PA2 | bidirectional | I/O; default function PA2, alternate functions USART1_TX, ADC01_IN2, TIMER1_CH2, TIMER4_CH2, TIMER8_CH0 (footnote 3, VG devices) and SPI0_IO2. |
| 26 | PA3 | bidirectional | I/O; default function PA3, alternate functions USART1_RX, ADC01_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1 (footnote 3, VG devices) and SPI0_IO3. |
| 27 | VSS_4 | power_in | Digital ground pin, default function VSS_4. |
| 28 | VDD_4 | power_in | Digital supply pin, default function VDD_4. |
| 29 | PA4 | bidirectional | I/O; default function PA4, alternate functions SPI0_NSS, USART1_CK, ADC01_IN4 and DAC_OUT0; remap SPI2_NSS and I2S2_WS. |
| 30 | PA5 | bidirectional | I/O; default function PA5, alternate functions SPI0_SCK, ADC01_IN5 and DAC_OUT1. |
| 31 | PA6 | bidirectional | I/O; default function PA6, alternate functions SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN (footnote 4), TIMER12_CH0 (footnote 3); remap TIMER0_BRKIN. |
| 32 | PA7 | bidirectional | I/O; default function PA7, alternate functions SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON (footnote 4), TIMER13_CH0 (footnote 3); remap TIMER0_CH0_ON. |
| 33 | PC4 | bidirectional | I/O; default function PC4, alternate function ADC01_IN14. |
| 34 | PC5 | bidirectional | I/O; default function PC5, alternate function ADC01_IN15. |
| 35 | PB0 | bidirectional | I/O; default function PB0, alternate functions ADC01_IN8, TIMER2_CH2 and TIMER7_CH1_ON (footnote 4); remap TIMER0_CH1_ON. |
| 36 | PB1 | bidirectional | I/O; default function PB1, alternate functions ADC01_IN9, TIMER2_CH3 and TIMER7_CH2_ON (footnote 4); remap TIMER0_CH2_ON. |
| 37 | PB2 | bidirectional | 5 V tolerant I/O; default functions PB2 and BOOT1. |
| 38 | PE7 | bidirectional | 5 V tolerant I/O; default function PE7, alternate function EXMC_D4; remap TIMER0_ETI. |
| 39 | PE8 | bidirectional | 5 V tolerant I/O; default function PE8, alternate function EXMC_D5; remap TIMER0_CH0_ON. |
| 40 | PE9 | bidirectional | 5 V tolerant I/O; default function PE9, alternate function EXMC_D6; remap TIMER0_CH0. |
| 41 | PE10 | bidirectional | 5 V tolerant I/O; default function PE10, alternate function EXMC_D7; remap TIMER0_CH1_ON. |
| 42 | PE11 | bidirectional | 5 V tolerant I/O; default function PE11, alternate function EXMC_D8; remap TIMER0_CH1. |
| 43 | PE12 | bidirectional | 5 V tolerant I/O; default function PE12, alternate function EXMC_D9; remap TIMER0_CH2_ON. |
| 44 | PE13 | bidirectional | 5 V tolerant I/O; default function PE13, alternate function EXMC_D10; remap TIMER0_CH2. |
| 45 | PE14 | bidirectional | 5 V tolerant I/O; default function PE14, alternate function EXMC_D11; remap TIMER0_CH3. |
| 46 | PE15 | bidirectional | 5 V tolerant I/O; default function PE15, alternate function EXMC_D12; remap TIMER0_BRKIN. |
| 47 | PB10 | bidirectional | 5 V tolerant I/O; default function PB10, alternate functions I2C1_SCL and USART2_TX; remap TIMER1_CH2. |
| 48 | PB11 | bidirectional | 5 V tolerant I/O; default function PB11, alternate functions I2C1_SDA and USART2_RX; remap TIMER1_CH3. |
| 49 | VSS_1 | power_in | Digital ground pin, default function VSS_1. |
| 50 | VDD_1 | power_in | Digital supply pin, default function VDD_1. |
| 51 | PB12 | bidirectional | 5 V tolerant I/O; default function PB12, alternate functions SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS and CAN1_RX. |
| 52 | PB13 | bidirectional | 5 V tolerant I/O; default function PB13, alternate functions SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK and CAN1_TX. |
| 53 | PB14 | bidirectional | 5 V tolerant I/O; default function PB14, alternate functions SPI1_MISO, USART2_RTS, TIMER0_CH1_ON and TIMER11_CH0 (footnote 3). |
| 54 | PB15 | bidirectional | 5 V tolerant I/O; default function PB15, alternate functions SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD and TIMER11_CH1 (footnote 3). |
| 55 | PD8 | bidirectional | 5 V tolerant I/O; default function PD8, alternate function EXMC_D13; remap USART2_TX. |
| 56 | PD9 | bidirectional | 5 V tolerant I/O; default function PD9, alternate function EXMC_D14; remap USART2_RX. |
| 57 | PD10 | bidirectional | 5 V tolerant I/O; default function PD10, alternate function EXMC_D15; remap USART2_CK. |
| 58 | PD11 | bidirectional | 5 V tolerant I/O; default function PD11, alternate function EXMC_A16; remap USART2_CTS. |
| 59 | PD12 | bidirectional | 5 V tolerant I/O; default function PD12, alternate function EXMC_A17; remap TIMER3_CH0 and USART2_RTS. |
| 60 | PD13 | bidirectional | 5 V tolerant I/O; default function PD13, alternate function EXMC_A18; remap TIMER3_CH1. |
| 61 | PD14 | bidirectional | 5 V tolerant I/O; default function PD14, alternate function EXMC_D0; remap TIMER3_CH2. |
| 62 | PD15 | bidirectional | 5 V tolerant I/O; default function PD15, alternate function EXMC_D1; remap TIMER3_CH3 and CTC_SYNC. |
| 63 | PC6 | bidirectional | 5 V tolerant I/O; default function PC6, alternate functions I2S1_MCK and TIMER7_CH0 (footnote 4); remap TIMER2_CH0. |
| 64 | PC7 | bidirectional | 5 V tolerant I/O; default function PC7, alternate functions I2S2_MCK and TIMER7_CH1 (footnote 4); remap TIMER2_CH1. |
| 65 | PC8 | bidirectional | 5 V tolerant I/O; default function PC8, alternate function TIMER7_CH2 (footnote 4); remap TIMER2_CH2. |
| 66 | PC9 | bidirectional | 5 V tolerant I/O; default function PC9, alternate function TIMER7_CH3 (footnote 4); remap TIMER2_CH3. |
| 67 | PA8 | bidirectional | 5 V tolerant I/O; default function PA8, alternate functions USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF and CTC_SYNC. |
| 68 | PA9 | bidirectional | 5 V tolerant I/O; default function PA9, alternate functions USART0_TX, TIMER0_CH1 and USBFS_VBUS. |
| 69 | PA10 | bidirectional | 5 V tolerant I/O; default function PA10, alternate functions USART0_RX, TIMER0_CH2 and USBFS_ID. |
| 70 | PA11 | bidirectional | 5 V tolerant I/O; default function PA11, alternate functions USART0_CTS, CAN0_RX, USBFS_DM and TIMER0_CH3. |
| 71 | PA12 | bidirectional | 5 V tolerant I/O; default function PA12, alternate functions USART0_RTS, USBFS_DP, CAN0_TX and TIMER0_ETI. |
| 72 | PA13 | bidirectional | 5 V tolerant I/O; default functions JTMS and SWDIO; remap PA13. |
| 73 | NC | unconnected | Not connected; the pin table gives no function for this pin. |
| 74 | VSS_2 | power_in | Digital ground pin, default function VSS_2. |
| 75 | VDD_2 | power_in | Digital supply pin, default function VDD_2. |
| 76 | PA14 | bidirectional | 5 V tolerant I/O; default functions JTCK and SWCLK; remap PA14. |
| 77 | PA15 | bidirectional | 5 V tolerant I/O; default function JTDI; alternate functions SPI2_NSS and I2S2_WS; remap TIMER1_CH0, TIMER1_ETI, PA15 and SPI0_NSS. |
| 78 | PC10 | bidirectional | 5 V tolerant I/O; default function PC10, alternate function UART3_TX; remap USART2_TX, SPI2_SCK and I2S2_CK. |
| 79 | PC11 | bidirectional | 5 V tolerant I/O; default function PC11, alternate function UART3_RX; remap USART2_RX and SPI2_MISO. |
| 80 | PC12 | bidirectional | 5 V tolerant I/O; default function PC12, alternate function UART4_TX; remap USART2_CK, SPI2_MOSI and I2S2_SD. |
| 81 | PD0 | bidirectional | 5 V tolerant I/O; default function PD0, alternate function EXMC_D2; remap CAN0_RX and OSCIN. |
| 82 | PD1 | bidirectional | 5 V tolerant I/O; default function PD1, alternate function EXMC_D3; remap CAN0_TX and OSCOUT. |
| 83 | PD2 | bidirectional | 5 V tolerant I/O; default function PD2, alternate functions TIMER2_ETI and UART4_RX. |
| 84 | PD3 | bidirectional | 5 V tolerant I/O; default function PD3, alternate function EXMC_CLK; remap USART1_CTS. |
| 85 | PD4 | bidirectional | 5 V tolerant I/O; default function PD4, alternate function EXMC_NOE; remap USART1_RTS. |
| 86 | PD5 | bidirectional | 5 V tolerant I/O; default function PD5, alternate function EXMC_NWE; remap USART1_TX. |
| 87 | PD6 | bidirectional | 5 V tolerant I/O; default function PD6, alternate function EXMC_NWAIT; remap USART1_RX. |
| 88 | PD7 | bidirectional | 5 V tolerant I/O; default function PD7, alternate functions EXMC_NE0 and EXMC_NCE1; remap USART1_CK. |
| 89 | PB3 | bidirectional | 5 V tolerant I/O; default function JTDO; alternate functions SPI2_SCK and I2S2_CK; remap PB3, TRACESWO, TIMER1_CH1 and SPI0_SCK. |
| 90 | PB4 | bidirectional | 5 V tolerant I/O; default function NJTRST; alternate function SPI2_MISO; remap TIMER2_CH0, PB4 and SPI0_MISO. |
| 91 | PB5 | bidirectional | I/O (no 5 V tolerance marked in the pin table); default function PB5, alternate functions I2C0_SMBA, SPI2_MOSI and I2S2_SD; remap TIMER2_CH1, SPI0_MOSI and CAN1_RX. |
| 92 | PB6 | bidirectional | 5 V tolerant I/O; default function PB6, alternate functions I2C0_SCL and TIMER3_CH0; remap USART0_TX, CAN1_TX and SPI0_IO2. |
| 93 | PB7 | bidirectional | 5 V tolerant I/O; default function PB7, alternate functions I2C0_SDA, TIMER3_CH1 and EXMC_NADV; remap USART0_RX and SPI0_IO3. |
| 94 | BOOT0 | input | Boot mode input pin with default function BOOT0. |
| 95 | PB8 | bidirectional | 5 V tolerant I/O; default function PB8, alternate functions TIMER3_CH2 and TIMER9_CH0 (footnote 3); remap I2C0_SCL and CAN0_RX. |
| 96 | PB9 | bidirectional | 5 V tolerant I/O; default function PB9, alternate functions TIMER3_CH3 and TIMER10_CH0 (footnote 3); remap I2C0_SDA and CAN0_TX. |
| 97 | PE0 | bidirectional | 5 V tolerant I/O; default function PE0, alternate functions TIMER3_ETI and EXMC_NBL0. |
| 98 | PE1 | bidirectional | 5 V tolerant I/O; default function PE1, alternate function EXMC_NBL1. |
| 99 | VSS_3 | power_in | Digital ground pin, default function VSS_3. |
| 100 | VDD_3 | power_in | Digital supply pin, default function VDD_3. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage on other I/O | VIN |  |  | 3.6 | V |  | 48 |
| Input voltage on 5V tolerant pin (cap) | VIN |  |  | 6.5 | V | Note (3): VIN maximum value cannot exceed 6.5 V | 48 |
| Variations between different VDD power pins | /ΔVDDX/ |  |  | 50 | mV |  | 48 |
| Variations between different ground pins | /VSSX −VSS/ |  |  | 50 | mV |  | 48 |
| Maximum current for GPIO pins | IIO | -25 |  | 25 | mA |  | 48 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 48 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 48 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 48 |
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V |  | 48 |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 48 |
| Battery supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 48 |
| AHB clock frequency | fHCLK |  |  | 120 | MHz |  | 49 |
| APB1 clock frequency | fAPB1 |  |  | 60 | MHz |  | 49 |
| APB2 clock frequency | fAPB2 |  |  | 120 | MHz |  | 49 |
| Crystal or ceramic frequency (HXTAL) | fHXTAL | 4 | 8 | 32 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 59 |
| IRC8M oscillator frequency accuracy, factory-trimmed | ACCIRC8M | -2.5 |  | 2.5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 61 |
| IRC8M oscillator frequency accuracy, factory-trimmed | ACCIRC8M | -1.8 |  | 1.8 | % | VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C | 61 |
| IRC8M oscillator frequency accuracy, factory-trimmed | ACCIRC8M | -1 |  | 1 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 61 |
| Low speed internal oscillator (IRC40K) frequency | fIRC40K | 20 | 40 | 45 | kHz | VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C | 61 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -4 |  | 5 | % | VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C | 62 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -3 |  | 3 | % | VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C | 62 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -2 |  | 2 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 62 |
| PLL input clock frequency | fPLLIN | 1 |  | 25 | MHz |  | 62 |
| PLL output clock frequency | fPLLOUT | 16 |  | 120 | MHz |  | 62 |
| PLL VCO output clock frequency | fVCO | 32 |  | 240 | MHz |  | 62 |
| PLL lock time | tLOCK |  |  | 300 | μs |  | 62 |
| Number of guaranteed program/erase cycles (Endurance) | PECYC | 100 |  |  | kcycles | TA = -40 °C ~ +85 °C | 64 |
| Word programming time | tPROG |  |  | 86 | μs | TA = -40°C ~ +85 °C | 64 |
| NRST input low level voltage | VIL(NRST) | -0.5 |  |  | V | VDD = VDDA = 2.6 V | 64 |
| Low level output voltage for an IO pin | VOL |  |  | 0.17 | V | IIO = +8 mA, VDD = 2.6 V | 65 |
| Low level output voltage for an IO pin | VOL |  |  | 0.16 | V | IIO = +8 mA, VDD = 3.3 V | 65 |
| Low level output voltage for an IO pin | VOL |  |  | 0.15 | V | IIO = +8 mA, VDD = 3.6 V | 65 |
| Low level output voltage for an IO pin | VOL |  |  | 0.49 | V | IIO = +20 mA, VDD = 2.6 V | 65 |
| Low level output voltage for an IO pin | VOL |  |  | 0.4 | V | IIO = +20 mA, VDD = 3.3 V | 65 |
| Low level output voltage for an IO pin | VOL |  |  | 0.34 | V | IIO = +20 mA, VDD = 3.6 V | 65 |
| High level output voltage for an IO pin | VOH | 2.4 |  |  | V | IIO = +8 mA, VDD = 2.6 V | 65 |
| High level output voltage for an IO pin | VOH | 3.15 |  |  | V | IIO = +8 mA, VDD = 3.3 V | 65 |
| High level output voltage for an IO pin | VOH | 3.44 |  |  | V | IIO = +8 mA, VDD = 3.6 V | 65 |
| High level output voltage for an IO pin | VOH | 2.02 |  |  | V | IIO = +20 mA, VDD = 2.6 V | 65 |
| High level output voltage for an IO pin | VOH | 2.8 |  |  | V | IIO = +20 mA, VDD = 3.3 V | 65 |
| Internal pull-up resistor | RPU | 30 | 40 | 50 | kΩ | All pins VIN = VSS | 65 |
| Internal pull-down resistor | RPD | 30 | 40 | 50 | kΩ | All pins VIN = VDD | 65 |
| Maximum frequency (IO_Speed = MAX) |  |  |  | 120 | MHz | GPIOx_CTL->MDy[1:0]=11 and GPIOx_SPDy=1; 2.6 ≤ VDD ≤ 3.6 V, CL = 10 pF | 66 |
| Maximum frequency (IO_Speed = MAX) |  |  |  | 100 | MHz | GPIOx_CTL->MDy[1:0]=11 and GPIOx_SPDy=1; 2.6 ≤ VDD ≤ 3.6 V, CL = 30 pF | 66 |
| Maximum frequency (IO_Speed = MAX) |  |  |  | 60 | MHz | GPIOx_CTL->MDy[1:0]=11 and GPIOx_SPDy=1; 2.6 ≤ VDD ≤ 3.6 V, CL = 50 pF | 66 |
| ADC operating voltage VREF+ positive reference voltage | VREF+ | 2.4 |  |  | V |  | 66 |
| ADC clock | fADC | 0.1 |  | 40 | MHz |  | 67 |
| External input impedance (RAIN) | RAIN |  |  | 32.9 | kΩ | See Equation 1 | 67 |
| Sampling time | ts | 0.0375 |  | 5.99 | μs | fADC = 40 MHz | 67 |
| Startup time | tSU |  |  | 1 | μs |  | 67 |
| Load resistance | RLOAD | 5 |  |  | kΩ | Resistive load with buffer ON | 68 |
| Differential non-linearity error | DNL | -3 |  | 3 | LSB | DAC in 12-bit mode | 69 |
| Integral non-linearity | INL | -4 |  | 4 | LSB | DAC in 12-bit mode | 69 |
| Human body model ESD voltage | VESD(HBM) |  |  | 4000 | V | TA = 25 °C; JESD22-A114 | 58 |
| Charge device model ESD voltage | VESD(CDM) |  |  | 800 | V | TA = 25 °C; JESD22-C101 | 58 |
| Static latch-up I-test | LU | -200 |  | 200 | mA | TA = 25 °C; JESD78 | 59 |
| Vsupply over voltage (latch-up) | Vsupply |  |  | 5.4 | V |  | 59 |

## CAD (KiCad official)

- Symbol: `GD32F305VGT6`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `gd32f305vgt6-etched.step` / `gd32f305vgt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32f305vgt6.step` / `gd32f305vgt6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588919091399184384) (83 pp, sha256 `b600f18e174fa334`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32f305vgt6-datasheet.pdf)