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GD32F305VET6
Public Made by Adomby adom
GigaDevice Semicon Beijing Microcontroller Units (MCUs/MPUs/SOCs), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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README
markdownGD32F305VET6
GigaDevice Semicon Beijing · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-100(14x14)
GD32F305VET6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant I/O, default PE2; alternate TRACECK, EXMC_A23. |
| 2 | PE3 | bidirectional | 5 V tolerant I/O, default PE3; alternate TRACED0, EXMC_A19. |
| 3 | PE4 | bidirectional | 5 V tolerant I/O, default PE4; alternate TRACED1, EXMC_A20. |
| 4 | PE5 | bidirectional | 5 V tolerant I/O, default PE5; alternate TRACED2, EXMC_A21; remap TIMER8_CH0 (GD32F305VG only). |
| 5 | PE6 | bidirectional | 5 V tolerant I/O, default PE6; alternate TRACED3, EXMC_A22; remap TIMER8_CH1 (GD32F305VG only). |
| 6 | VBAT | power_in | Backup battery supply pin. |
| 7 | PC13-TAMPER-RTC | bidirectional | I/O, default PC13; alternate TAMPER-RTC. |
| 8 | PC14-OSC32IN | bidirectional | I/O, default PC14; alternate OSC32IN. |
| 9 | PC15-OSC32OUT | bidirectional | I/O, default PC15; alternate OSC32OUT. |
| 10 | VSS_5 | power_in | Ground pin VSS_5. |
| 11 | VDD_5 | power_in | Digital supply pin VDD_5. |
| 12 | OSCIN | input | Oscillator input, default OSCIN; remap PD0. |
| 13 | OSCOUT | output | Oscillator output, default OSCOUT; remap PD1. |
| 14 | NRST | bidirectional | Reset pin, default NRST. |
| 15 | PC0 | bidirectional | I/O, default PC0; alternate ADC01_IN10. |
| 16 | PC1 | bidirectional | I/O, default PC1; alternate ADC01_IN11. |
| 17 | PC2 | bidirectional | I/O, default PC2; alternate ADC01_IN12. |
| 18 | PC3 | bidirectional | I/O, default PC3; alternate ADC01_IN13. |
| 19 | VSSA | power_in | Analog ground pin. |
| 20 | VREF- | power_in | Negative ADC/DAC reference voltage pin. |
| 21 | VREF+ | power_in | Positive ADC/DAC reference voltage pin. |
| 22 | VDDA | power_in | Analog supply pin. |
| 23 | PA0-WKUP | bidirectional | I/O, default PA0; alternate WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI (VE/G only). |
| 24 | PA1 | bidirectional | I/O, default PA1; alternate USART1_RTS, ADC01_IN1, TIMER1_CH1, TIMER4_CH1. |
| 25 | PA2 | bidirectional | I/O, default PA2; alternate USART1_TX, ADC01_IN2, TIMER1_CH2, TIMER4_CH2, TIMER8_CH0 (VG only), SPI0_IO2. |
| 26 | PA3 | bidirectional | I/O, default PA3; alternate USART1_RX, ADC01_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1 (VG only), SPI0_IO3. |
| 27 | VSS_4 | power_in | Ground pin VSS_4. |
| 28 | VDD_4 | power_in | Digital supply pin VDD_4. |
| 29 | PA4 | bidirectional | I/O, default PA4; alternate SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0; remap SPI2_NSS, I2S2_WS. |
| 30 | PA5 | bidirectional | I/O, default PA5; alternate SPI0_SCK, ADC01_IN5, DAC_OUT1. |
| 31 | PA6 | bidirectional | I/O, default PA6; alternate SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN, TIMER12_CH0 (VG only); remap TIMER0_BRKIN. |
| 32 | PA7 | bidirectional | I/O, default PA7; alternate SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON, TIMER13_CH0 (VG only); remap TIMER0_CH0_ON. |
| 33 | PC4 | bidirectional | I/O, default PC4; alternate ADC01_IN14. |
| 34 | PC5 | bidirectional | I/O, default PC5; alternate ADC01_IN15. |
| 35 | PB0 | bidirectional | I/O, default PB0; alternate ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON; remap TIMER0_CH1_ON. |
| 36 | PB1 | bidirectional | I/O, default PB1; alternate ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON; remap TIMER0_CH2_ON. |
| 37 | PB2 | bidirectional | 5 V tolerant I/O, default PB2, BOOT1. |
| 38 | PE7 | bidirectional | 5 V tolerant I/O, default PE7; alternate EXMC_D4; remap TIMER0_ETI. |
| 39 | PE8 | bidirectional | 5 V tolerant I/O, default PE8; alternate EXMC_D5; remap TIMER0_CH0_ON. |
| 40 | PE9 | bidirectional | 5 V tolerant I/O, default PE9; alternate EXMC_D6; remap TIMER0_CH0. |
| 41 | PE10 | bidirectional | 5 V tolerant I/O, default PE10; alternate EXMC_D7; remap TIMER0_CH1_ON. |
| 42 | PE11 | bidirectional | 5 V tolerant I/O, default PE11; alternate EXMC_D8; remap TIMER0_CH1. |
| 43 | PE12 | bidirectional | 5 V tolerant I/O, default PE12; alternate EXMC_D9; remap TIMER0_CH2_ON. |
| 44 | PE13 | bidirectional | 5 V tolerant I/O, default PE13; alternate EXMC_D10; remap TIMER0_CH2. |
| 45 | PE14 | bidirectional | 5 V tolerant I/O, default PE14; alternate EXMC_D11; remap TIMER0_CH3. |
| 46 | PE15 | bidirectional | 5 V tolerant I/O, default PE15; alternate EXMC_D12; remap TIMER0_BRKIN. |
| 47 | PB10 | bidirectional | 5 V tolerant I/O, default PB10; alternate I2C1_SCL, USART2_TX; remap TIMER1_CH2. |
| 48 | PB11 | bidirectional | 5 V tolerant I/O, default PB11; alternate I2C1_SDA, USART2_RX; remap TIMER1_CH3. |
| 49 | VSS_1 | power_in | Ground pin VSS_1. |
| 50 | VDD_1 | power_in | Digital supply pin VDD_1. |
| 51 | PB12 | bidirectional | 5 V tolerant I/O, default PB12; alternate SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS, CAN1_RX. |
| 52 | PB13 | bidirectional | 5 V tolerant I/O, default PB13; alternate SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK, CAN1_TX. |
| 53 | PB14 | bidirectional | 5 V tolerant I/O, default PB14; alternate SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0 (VG only). |
| 54 | PB15 | bidirectional | 5 V tolerant I/O, default PB15; alternate SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1 (VG only). |
| 55 | PD8 | bidirectional | 5 V tolerant I/O, default PD8; alternate EXMC_D13; remap USART2_TX. |
| 56 | PD9 | bidirectional | 5 V tolerant I/O, default PD9; alternate EXMC_D14; remap USART2_RX. |
| 57 | PD10 | bidirectional | 5 V tolerant I/O, default PD10; alternate EXMC_D15; remap USART2_CK. |
| 58 | PD11 | bidirectional | 5 V tolerant I/O, default PD11; alternate EXMC_A16; remap USART2_CTS. |
| 59 | PD12 | bidirectional | 5 V tolerant I/O, default PD12; alternate EXMC_A17; remap TIMER3_CH0, USART2_RTS. |
| 60 | PD13 | bidirectional | 5 V tolerant I/O, default PD13; alternate EXMC_A18; remap TIMER3_CH1. |
| 61 | PD14 | bidirectional | 5 V tolerant I/O, default PD14; alternate EXMC_D0; remap TIMER3_CH2. |
| 62 | PD15 | bidirectional | 5 V tolerant I/O, default PD15; alternate EXMC_D1; remap TIMER3_CH3, CTC_SYNC. |
| 63 | PC6 | bidirectional | 5 V tolerant I/O, default PC6; alternate I2S1_MCK, TIMER7_CH0 (VE/G only); remap TIMER2_CH0. |
| 64 | PC7 | bidirectional | 5 V tolerant I/O, default PC7; alternate I2S2_MCK, TIMER7_CH1 (VE/G only); remap TIMER2_CH1. |
| 65 | PC8 | bidirectional | 5 V tolerant I/O, default PC8; alternate TIMER7_CH2 (VE/G only); remap TIMER2_CH2. |
| 66 | PC9 | bidirectional | 5 V tolerant I/O, default PC9; alternate TIMER7_CH3 (VE/G only); remap TIMER2_CH3. |
| 67 | PA8 | bidirectional | 5 V tolerant I/O, default PA8; alternate USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF, CTC_SYNC. |
| 68 | PA9 | bidirectional | 5 V tolerant I/O, default PA9; alternate USART0_TX, TIMER0_CH1, USBFS_VBUS. |
| 69 | PA10 | bidirectional | 5 V tolerant I/O, default PA10; alternate USART0_RX, TIMER0_CH2, USBFS_ID. |
| 70 | PA11 | bidirectional | 5 V tolerant I/O, default PA11; alternate USART0_CTS, CAN0_RX, USBFS_DM, TIMER0_CH3. |
| 71 | PA12 | bidirectional | 5 V tolerant I/O, default PA12; alternate USART0_RTS, USBFS_DP, CAN0_TX, TIMER0_ETI. |
| 72 | PA13 | bidirectional | 5 V tolerant I/O, default JTMS, SWDIO; remap PA13. |
| 73 | NC | unconnected | No connect. |
| 74 | VSS_2 | power_in | Ground pin VSS_2. |
| 75 | VDD_2 | power_in | Digital supply pin VDD_2. |
| 76 | PA14 | bidirectional | 5 V tolerant I/O, default JTCK, SWCLK; remap PA14. |
| 77 | PA15 | bidirectional | 5 V tolerant I/O, default JTDI; alternate SPI2_NSS, I2S2_WS; remap TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS. |
| 78 | PC10 | bidirectional | 5 V tolerant I/O, default PC10; alternate UART3_TX; remap USART2_TX, SPI2_SCK, I2S2_CK. |
| 79 | PC11 | bidirectional | 5 V tolerant I/O, default PC11; alternate UART3_RX; remap USART2_RX, SPI2_MISO. |
| 80 | PC12 | bidirectional | 5 V tolerant I/O, default PC12; alternate UART4_TX; remap USART2_CK, SPI2_MOSI, I2S2_SD. |
| 81 | PD0 | bidirectional | 5 V tolerant I/O, default PD0; alternate EXMC_D2; remap CAN0_RX, OSCIN. |
| 82 | PD1 | bidirectional | 5 V tolerant I/O, default PD1; alternate EXMC_D3; remap CAN0_TX, OSCOUT. |
| 83 | PD2 | bidirectional | 5 V tolerant I/O, default PD2; alternate TIMER2_ETI, UART4_RX. |
| 84 | PD3 | bidirectional | 5 V tolerant I/O, default PD3; alternate EXMC_CLK; remap USART1_CTS. |
| 85 | PD4 | bidirectional | 5 V tolerant I/O, default PD4; alternate EXMC_NOE; remap USART1_RTS. |
| 86 | PD5 | bidirectional | 5 V tolerant I/O, default PD5; alternate EXMC_NWE; remap USART1_TX. |
| 87 | PD6 | bidirectional | 5 V tolerant I/O, default PD6; alternate EXMC_NWAIT; remap USART1_RX. |
| 88 | PD7 | bidirectional | 5 V tolerant I/O, default PD7; alternate EXMC_NE0, EXMC_NCE1; remap USART1_CK. |
| 89 | PB3 | bidirectional | 5 V tolerant I/O, default JTDO; alternate SPI2_SCK, I2S2_CK; remap PB3, TRACESWO, TIMER1_CH1, SPI0_SCK. |
| 90 | PB4 | bidirectional | 5 V tolerant I/O, default NJTRST; alternate SPI2_MISO; remap TIMER2_CH0, PB4, SPI0_MISO. |
| 91 | PB5 | bidirectional | I/O, default PB5; alternate I2C0_SMBA, SPI2_MOSI, I2S2_SD; remap TIMER2_CH1, SPI0_MOSI, CAN1_RX. |
| 92 | PB6 | bidirectional | 5 V tolerant I/O, default PB6; alternate I2C0_SCL, TIMER3_CH0; remap USART0_TX, CAN1_TX, SPI0_IO2. |
| 93 | PB7 | bidirectional | 5 V tolerant I/O, default PB7; alternate I2C0_SDA, TIMER3_CH1, EXMC_NADV; remap USART0_RX, SPI0_IO3. |
| 94 | BOOT0 | input | Boot mode selection input, default BOOT0. |
| 95 | PB8 | bidirectional | 5 V tolerant I/O, default PB8; alternate TIMER3_CH2, TIMER9_CH0 (VG only); remap I2C0_SCL, CAN0_RX. |
| 96 | PB9 | bidirectional | 5 V tolerant I/O, default PB9; alternate TIMER3_CH3, TIMER10_CH0 (VG only); remap I2C0_SDA, CAN0_TX. |
| 97 | PE0 | bidirectional | 5 V tolerant I/O, default PE0; alternate TIMER3_ETI, EXMC_NBL0. |
| 98 | PE1 | bidirectional | 5 V tolerant I/O, default PE1; alternate EXMC_NBL1. |
| 99 | VSS_3 | power_in | Ground pin VSS_3. |
| 100 | VDD_3 | power_in | Digital supply pin VDD_3. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-100(14x14) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 100 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External voltage range | VDD | -0.3 | 3.6 | V | VSS - 0.3 to VSS + 3.6 | 48 | |
| External analog supply voltage | VDDA | -0.3 | 3.6 | V | VSSA - 0.3 to VSSA + 3.6 | 48 | |
| External battery supply voltage | VBAT | -0.3 | 3.6 | V | VSS - 0.3 to VSS + 3.6 | 48 | |
| Input voltage on other I/O | VIN | -0.3 | 3.6 | V | VSS - 0.3 to 3.6 | 48 | |
| Variations between different VDD power pins | /ΔVDDX/ | 50 | mV | 48 | |||
| Variations between different ground pins | /VSSX −VSS/ | 50 | mV | 48 | |||
| Maximum current for GPIO pins | IIO | -25 | 25 | mA | ±25 | 48 | |
| Operating temperature range | TA | -40 | 85 | °C | 48 | ||
| Power dissipation of LQFP100 | PD | 848 | mW | TA = 85°C | 48 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 48 | ||
| Maximum junction temperature | TJ | 125 | °C | 48 | |||
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V | 48 | |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 48 |
| Battery supply voltage | VBAT | 1.8 | 3.6 | V | 48 | ||
| AHB clock frequency | fHCLK | 120 | MHz | 49 | |||
| APB1 clock frequency | fAPB1 | 60 | MHz | 49 | |||
| APB2 clock frequency | fAPB2 | 120 | MHz | 49 | |||
| VDD fall time rate | tVDD | 20 | μs/V | 49 | |||
| Thermal resistance junction-to-ambient LQFP100 | θJA | 47.19 | °C/W | Natural convection, 2S2P PCB | 87 | ||
| Thermal resistance junction-to-board LQFP100 | θJB | 27.43 | °C/W | Cold plate, 2S2P PCB | 87 | ||
| Thermal resistance junction-to-case LQFP100 | θJC | 8.57 | °C/W | Cold plate, 2S2P PCB | 88 | ||
| Crystal or ceramic frequency (HXTAL) | fHXTAL | 4 | 8 | 32 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 59 |
| External clock frequency (HXTAL bypass) | fHXTAL_ext | 1 | 50 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 59 | |
| OSCIN high or low time | tH/L(HXTAL) | 5 | ns | 60 | |||
| OSCIN rise or fall time | tR/F(HXTAL) | 10 | ns | 60 | |||
| HXTAL bypass duty cycle | Ducy(HXTAL) | 40 | 60 | % | 60 | ||
| LXTAL bypass external clock frequency | fLXTAL_ext | 32.768 | 1000 | kHz | VDD = 3.3 V | 61 | |
| IRC8M accuracy, factory-trimmed | ACCIRC8M | -2.5 | 2.5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 61 | |
| IRC8M accuracy, factory-trimmed | ACCIRC8M | -1 | 1 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 61 | |
| IRC40K frequency | fIRC40K | 20 | 40 | 45 | kHz | VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C | 62 |
| IRC48M accuracy, factory-trimmed | ACCIRC48M | -4 | 5 | % | VDD = VDDA = 3.3 V, TA = -40°C ~+85 °C | 62 | |
| IRC48M accuracy, factory-trimmed | ACCIRC48M | -2 | 2 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 62 | |
| PLL output clock frequency | fPLLOUT | 16 | 120 | MHz | 63 | ||
| Flash endurance | PECYC | 100 | kcycles | TA = -40 °C ~ +85 °C | 64 | ||
| Word programming time | tPROG | 47.5 | 215 | μs | TA = -40°C ~ +85 °C | 64 | |
| Page erase time | tERASE | 45 | 800 | ms | TA = -40°C ~ +85 °C | 64 | |
| Mass erase time | tMERASE(512K) | 4 | 48 | s | TA = -40°C ~ +85 °C | 64 | |
| Internal pull-up resistor (all pins) | RPU | 30 | 40 | 50 | kΩ | VIN = VSS | 66 |
| Internal pull-down resistor (all pins) | RPD | 30 | 40 | 50 | kΩ | VIN = VDD | 66 |
| Low level output voltage | VOL | 0.16 | V | IIO = +8mA, VDD = 3.3 V | 66 | ||
| Low level output voltage | VOL | 0.4 | V | IIO = +20mA, VDD = 3.3 V | 66 | ||
| High level output voltage | VOH | 3.15 | V | IIO = +8mA, VDD = 3.3 V | 66 | ||
| High level output voltage | VOH | 2.8 | V | IIO = +20mA, VDD = 3.3 V | 66 | ||
| ADC operating voltage | VDDA | 2.6 | 3.3 | 3.6 | V | 67 | |
| ADC clock | fADC | 0.1 | 40 | MHz | 67 | ||
| External input impedance | RAIN | 32.9 | kΩ | See Equation 1 | 67 | ||
| Input sampling capacitance | CADC | 5.5 | pF | No pin/pad capacitance included | 67 | ||
| Positive reference voltage | VREF+ | 2.6 | 3.6 | V | 67 | ||
| DAC load resistance | RLOAD | 5 | kΩ | Resistive load with buffer ON | 69 | ||
| DAC differential non-linearity | DNL | -5 | 5 | LSB | DAC in 12-bit mode | 69 | |
| DAC integral non-linearity | INL | -4 | 4 | LSB | DAC in 12-bit mode | 69 | |
| DAC offset error | Offset | -12 | 12 | LSB | DAC in 12-bit mode | 69 | |
| DAC gain error | GE | -0.5 | 0.5 | % | DAC in 12-bit mode | 69 | |
| SPI clock frequency | fSCK | 30 | MHz | 71 | |||
| ESD voltage HBM | VESD(HBM) | 4000 | V | TA = 25 °C; JS-001-2017 | 59 | ||
| ESD voltage CDM | VESD(CDM) | 750 | V | TA = 25 °C; JS-002-2018 | 59 | ||
| Supply current (Run mode) | IDD+IDDA | 45.1 | mA | VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock = 120 MHz, All peripherals enabled | 49 |
CAD (KiCad official)
- Symbol:
GD32F305VET6 - Footprint:
Package_QFP:LQFP-100_14x14mm_P0.5mm - 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files:
gd32f305vet6-etched.step/gd32f305vet6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gd32f305vet6.step/gd32f305vet6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice Semicon Beijing datasheet (91 pp, sha256
2c2b16160f8ae1d7, retrieved 2026-10-22, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).