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GD32F305RET6

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GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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GD32F305RET6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

GD32F305RET6 from GigaDevice Semicon Beijing, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VBAT power_in Default function VBAT, the backup-domain power supply pin with no alternate function listed.
2 PC13-TAMPER-RTC bidirectional Default function PC13, with alternate function TAMPER-RTC.
3 PC14-OSC32IN bidirectional Default function PC14, with alternate function OSC32IN for the low-speed crystal input.
4 PC15-OSC32OUT bidirectional Default function PC15, with alternate function OSC32OUT for the low-speed crystal output.
5 OSCIN input Default function OSCIN for the high-speed crystal input, remappable to PD0, which cannot be used for EXTI in this package.
6 OSCOUT output Default function OSCOUT for the high-speed crystal output, remappable to PD1, which cannot be used for EXTI in this package.
7 NRST bidirectional Default function NRST, the reset pin listed as I/O in the table.
8 PC0 bidirectional Default function PC0, with alternate function ADC01_IN10.
9 PC1 bidirectional Default function PC1, with alternate function ADC01_IN11.
10 PC2 bidirectional Default function PC2, with alternate function ADC01_IN12.
11 PC3 bidirectional Default function PC3, with alternate function ADC01_IN13.
12 VSSA power_in Default function VSSA, the analog ground pin.
13 VDDA power_in Default function VDDA, the analog supply pin.
14 PA0-WKUP bidirectional Default function PA0, with alternate functions WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0 and TIMER7_ETI (TIMER7_ETI available on RE/G devices).
15 PA1 bidirectional Default function PA1, with alternate functions USART1_RTS, ADC01_IN1, TIMER1_CH1 and TIMER4_CH1.
16 PA2 bidirectional Default function PA2, with alternate functions USART1_TX, ADC01_IN2, TIMER1_CH2, TIMER4_CH2 and SPI0_IO2.
17 PA3 bidirectional Default function PA3, with alternate functions USART1_RX, ADC01_IN3, TIMER1_CH3, TIMER4_CH3 and SPI0_IO3.
18 VSS_4 power_in Ground pin VSS_4.
19 VDD_4 power_in Supply pin VDD_4.
20 PA4 bidirectional Default function PA4, with alternate functions SPI0_NSS, USART1_CK, ADC01_IN4 and DAC_OUT0; remap SPI2_NSS and I2S2_WS.
21 PA5 bidirectional Default function PA5, with alternate functions SPI0_SCK, ADC01_IN5 and DAC_OUT1.
22 PA6 bidirectional Default function PA6, with alternate functions SPI0_MISO, ADC01_IN6, TIMER2_CH0 and TIMER7_BRKIN (RE/G devices); remap TIMER0_BRKIN.
23 PA7 bidirectional Default function PA7, with alternate functions SPI0_MOSI, ADC01_IN7, TIMER2_CH1 and TIMER7_CH0_ON (RE/G devices); remap TIMER0_CH0_ON.
24 PC4 bidirectional Default function PC4, with alternate function ADC01_IN14.
25 PC5 bidirectional Default function PC5, with alternate function ADC01_IN15.
26 PB0 bidirectional Default function PB0, with alternate functions ADC01_IN8, TIMER2_CH2 and TIMER7_CH1_ON (RE/G devices); remap TIMER0_CH1_ON.
27 PB1 bidirectional Default function PB1, with alternate functions ADC01_IN9, TIMER2_CH3 and TIMER7_CH2_ON (RE/G devices); remap TIMER0_CH2_ON.
28 PB2 bidirectional 5 V tolerant pin with default function PB2, which also serves as BOOT1.
29 PB10 bidirectional 5 V tolerant pin with default function PB10, alternate functions I2C1_SCL and USART2_TX, and remap TIMER1_CH2.
30 PB11 bidirectional 5 V tolerant pin with default function PB11, alternate functions I2C1_SDA and USART2_RX, and remap TIMER1_CH3.
31 VSS_1 power_in Ground pin VSS_1.
32 VDD_1 power_in Supply pin VDD_1.
33 PB12 bidirectional 5 V tolerant pin with default function PB12 and alternate functions SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS and CAN1_RX.
34 PB13 bidirectional 5 V tolerant pin with default function PB13 and alternate functions SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK and CAN1_TX.
35 PB14 bidirectional 5 V tolerant pin with default function PB14 and alternate functions SPI1_MISO, USART2_RTS and TIMER0_CH1_ON.
36 PB15 bidirectional 5 V tolerant pin with default function PB15 and alternate functions SPI1_MOSI, TIMER0_CH2_ON and I2S1_SD.
37 PC6 bidirectional 5 V tolerant pin with default function PC6, alternate functions I2S1_MCK and TIMER7_CH0 (RE/G devices), and remap TIMER2_CH0.
38 PC7 bidirectional 5 V tolerant pin with default function PC7, alternate functions I2S2_MCK and TIMER7_CH1 (RE/G devices), and remap TIMER2_CH1.
39 PC8 bidirectional 5 V tolerant pin with default function PC8, alternate function TIMER7_CH2 (RE/G devices), and remap TIMER2_CH2.
40 PC9 bidirectional 5 V tolerant pin with default function PC9, alternate function TIMER7_CH3 (RE/G devices), and remap TIMER2_CH3.
41 PA8 bidirectional 5 V tolerant pin with default function PA8 and alternate functions USART0_CK, TIMER0_CH0, CK_OUT0, USBFS_SOF and CTC_SYNC.
42 PA9 bidirectional 5 V tolerant pin with default function PA9 and alternate functions USART0_TX, TIMER0_CH1 and USBFS_VBUS.
43 PA10 bidirectional 5 V tolerant pin with default function PA10 and alternate functions USART0_RX, TIMER0_CH2 and USBFS_ID.
44 PA11 bidirectional 5 V tolerant pin with default function PA11 and alternate functions USART0_CTS, CAN0_RX, USBFS_DM and TIMER0_CH3.
45 PA12 bidirectional 5 V tolerant pin with default function PA12 and alternate functions USART0_RTS, USBFS_DP, CAN0_TX and TIMER0_ETI.
46 PA13 bidirectional 5 V tolerant pin with default function JTMS/SWDIO, remappable to PA13.
47 VSS_2 power_in Ground pin VSS_2.
48 VDD_2 power_in Supply pin VDD_2.
49 PA14 bidirectional 5 V tolerant pin with default function JTCK/SWCLK, remappable to PA14.
50 PA15 bidirectional 5 V tolerant pin with default function JTDI and alternate functions SPI2_NSS and I2S2_WS; remap TIMER1_CH0, TIMER1_ETI, PA15 and SPI0_NSS.
51 PC10 bidirectional 5 V tolerant pin with default function PC10, alternate function UART3_TX, and remap USART2_TX, SPI2_SCK and I2S2_CK.
52 PC11 bidirectional 5 V tolerant pin with default function PC11, alternate function UART3_RX, and remap USART2_RX and SPI2_MISO.
53 PC12 bidirectional 5 V tolerant pin with default function PC12, alternate function UART4_TX, and remap USART2_CK, SPI2_MOSI and I2S2_SD.
54 PD2 bidirectional 5 V tolerant pin with default function PD2 and alternate functions TIMER2_ETI and UART4_RX.
55 PB3 bidirectional 5 V tolerant pin with default function JTDO and alternate functions SPI2_SCK and I2S2_CK; remap PB3, TRACESWO, TIMER1_CH1 and SPI0_SCK.
56 PB4 bidirectional 5 V tolerant pin with default function NJTRST and alternate function SPI2_MISO; remap TIMER2_CH0, PB4 and SPI0_MISO.
57 PB5 bidirectional Pin with default function PB5 and alternate functions I2C0_SMBA, SPI2_MOSI and I2S2_SD; remap TIMER2_CH1, SPI0_MOSI and CAN1_RX.
58 PB6 bidirectional 5 V tolerant pin with default function PB6 and alternate functions I2C0_SCL and TIMER3_CH0; remap USART0_TX, CAN1_TX and SPI0_IO2.
59 PB7 bidirectional 5 V tolerant pin with default function PB7 and alternate functions I2C0_SDA and TIMER3_CH1; remap USART0_RX and SPI0_IO3.
60 BOOT0 input Input pin with default function BOOT0.
61 PB8 bidirectional 5 V tolerant pin with default function PB8 and alternate function TIMER3_CH2; remap I2C0_SCL and CAN0_RX.
62 PB9 bidirectional 5 V tolerant pin with default function PB9 and alternate function TIMER3_CH3; remap I2C0_SDA and CAN0_TX.
63 VSS_3 power_in Ground pin VSS_3.
64 VDD_3 power_in Supply pin VDD_3.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-64(10x10)
Category Embedded Processors & Controllers
Pins 64

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD, external voltage range (referenced to VSS) VDD -0.3 3.6 V Printed as VSS - 0.3 / VSS + 3.6 48
Analog supply voltage VDDA (referenced to VSSA) VDDA -0.3 3.6 V Printed as VSSA - 0.3 / VSSA + 3.6 48
External battery supply voltage (referenced to VSS) VBAT -0.3 3.6 V Printed as VSS - 0.3 / VSS + 3.6 48
Input voltage on 5V tolerant pin VIN -0.3 6.5 V 5V tolerant pin; printed as VDD + 3.6, but VIN must not exceed 6.5 V (note 3) 48
Input voltage on other I/O VIN -0.3 3.6 V Other I/O pins 48
Variations between different VDD power pins /ΔVDDX/ 50 mV 48
Variations between different ground pins /VSSX −VSS/ 50 mV 48
Maximum current for GPIO pins IIO -25 25 mA Printed as ±25 mA 48
Operating temperature range TA -40 85 °C 48
Storage temperature range TSTG -55 150 °C 48
Maximum junction temperature TJ 125 °C 48
Supply voltage VDD 2.6 3.3 3.6 V 48
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 48
Battery supply voltage VBAT 1.8 3.6 V 48
AHB clock frequency fHCLK 120 MHz 49
APB1 clock frequency fAPB1 60 MHz 49
APB2 clock frequency fAPB2 120 MHz 49
VDD rise time rate tVDD 0 μs/V Printed max is ∞ (no finite value) 49
VDD fall time rate tVDD 20 μs/V Printed max is ∞ (no finite value) 49
Electrostatic discharge voltage (human body model) VESD(HBM) 4000 V TA = 25 °C; JESD22-A114 58
Electrostatic discharge voltage (charge device model) VESD(CDM) 800 V TA = 25 °C; JESD22-C101 58
Static latch-up I-test LU -200 200 mA TA = 25 °C; JESD78; printed as ±200 mA 59
Supply overvoltage for latch-up test Vsupply 5.4 V 59
Crystal or ceramic frequency (HXTAL) fHXTAL 4 8 32 MHz 2.6 V ≤ VDD ≤ 3.6 V 59
Recommended matching capacitance on OSCIN and OSCOUT CHXTAL 20 30 pF 59
Crystal or ceramic duty cycle (HXTAL) Ducy(HXTAL) 30 50 70 % 59
External clock source or oscillator frequency (HXTAL bypass) fHXTAL_ext 1 50 MHz 2.6 V ≤ VDD ≤ 3.6 V 59
OSCIN high or low time (HXTAL bypass) tH/L(HXTAL) 5 ns 59
OSCIN rise or fall time (HXTAL bypass) tR/F(HXTAL) 10 ns 59
Duty cycle (HXTAL bypass) Ducy(HXTAL) 40 60 % 59
Crystal or ceramic duty cycle (LXTAL) Ducy(LXTAL) 30 70 % 60
External clock source or oscillator frequency (LXTAL bypass) fLXTAL_ext 32.768 1000 kHz VDD = 3.3 V 60
OSC32IN high or low time (LXTAL bypass) tH/L(LXTAL) 450 ns 60
OSC32IN rise or fall time (LXTAL bypass) tR/F(LXTAL) 50 ns 60
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -2.5 2.5 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 61
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -1.8 1.8 % VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C 61
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -1 1 % VDD = VDDA = 3.3 V, TA = 25 °C 61
IRC8M oscillator duty cycle DucyIRC8M 45 50 55 % VDD = VDDA = 3.3 V 61
Low speed internal oscillator (IRC40K) frequency fIRC40K 20 40 45 kHz VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C 61
IRC48M oscillator frequency accuracy, factory-trimmed ACCIRC48M -4 5 % VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C 62
IRC48M oscillator frequency accuracy, factory-trimmed ACCIRC48M -3 3 % VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C 62
IRC48M oscillator frequency accuracy, factory-trimmed ACCIRC48M -2 2 % VDD = VDDA = 3.3 V, TA = 25 °C 62
IRC48M oscillator duty cycle DIRC48M 45 50 55 % VDD = VDDA = 3.3 V 62
PLL input clock frequency fPLLIN 1 25 MHz 62
PLL output clock frequency fPLLOUT 16 120 MHz 62
PLL VCO output clock frequency fVCO 32 240 MHz 62
PLL lock time tLOCK 300 μs 62
Number of guaranteed program/erase cycles before failure (Endurance) PECYC 100 kcycles TA = -40 °C ~ +85 °C 64
Word programming time tPROG 37.5 86 μs TA = -40°C ~ +85 °C 64
Page erase time tERASE 45 300 ms TA = -40°C ~ +85 °C; printed max 200 ms for <50K cycles and 300 ms for >50K & <100K cycles; 300 ms is the larger value 64
Mass erase time (512K flash) tMERASE(512K) 4 32 s TA = -40°C ~ +85 °C; printed max 19.2 s for <50K cycles and 32 s for >50K & <100K cycles; 32 s is the larger value 64
Low level output voltage for an IO pin (IIO = +8mA) VOL 0.17 V VDD = 2.6 V, IIO = +8mA 65
Low level output voltage for an IO pin (IIO = +8mA) VOL 0.16 V VDD = 3.3 V, IIO = +8mA 65
Low level output voltage for an IO pin (IIO = +8mA) VOL 0.15 V VDD = 3.6 V, IIO = +8mA 65
High level output voltage for an IO pin (IIO = +8mA) VOH 2.4 V VDD = 2.6 V, IIO = +8mA 65
High level output voltage for an IO pin (IIO = +8mA) VOH 3.15 V VDD = 3.3 V, IIO = +8mA 65
High level output voltage for an IO pin (IIO = +8mA) VOH 3.44 V VDD = 3.6 V, IIO = +8mA 65
Internal pull-up resistor (all pins except PA10) RPU 30 40 50 kΩ All pins VIN = VSS 65
Internal pull-down resistor (all pins except PA10) RPD 30 40 50 kΩ All pins VIN = VDD 65

CAD (KiCad official)

  • Symbol: GD32F305RET6
  • Footprint: Package_QFP:LQFP-64_10x10mm_P0.5mm
  • 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
  • 3D model files: gd32f305ret6-etched.step / gd32f305ret6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f305ret6.step / gd32f305ret6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (83 pp, sha256 b600f18e174fa334, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF