# GD32F303VGT6

**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F303VGT6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | Default function PE2 with alternates TRACECK and EXMC_A23; 5 V tolerant (5VT) I/O. |
| 2 | PE3 | bidirectional | Default function PE3 with alternates TRACED0 and EXMC_A19; 5 V tolerant (5VT) I/O. |
| 3 | PE4 | bidirectional | Default function PE4 with alternates TRACED1 and EXMC_A20; 5 V tolerant (5VT) I/O. |
| 4 | PE5 | bidirectional | Default function PE5 with alternates TRACED2 and EXMC_A21; remap TIMER8_CH0 (footnote 3, available in VG/I/K devices); 5 V tolerant (5VT) I/O. |
| 5 | PE6 | bidirectional | Default function PE6 with alternates TRACED3 and EXMC_A22; remap TIMER8_CH1 (footnote 3, available in VG/I/K devices); 5 V tolerant (5VT) I/O. |
| 6 | VBAT | power_in | Default function VBAT backup supply pin; the pin table gives no voltage limit. |
| 7 | PC13-TAMPER-RTC | bidirectional | Default function PC13 with alternate TAMPER-RTC; no 5 V tolerance level is listed in the pin table. |
| 8 | PC14-OSC32IN | bidirectional | Default function PC14 with alternate OSC32IN (low-speed crystal input); no 5 V tolerance level is listed in the pin table. |
| 9 | PC15-OSC32OUT | bidirectional | Default function PC15 with alternate OSC32OUT (low-speed crystal output); no 5 V tolerance level is listed in the pin table. |
| 10 | VSS_5 | power_in | Ground pin (default function VSS_5); the pin table gives no further limits. |
| 11 | VDD_5 | power_in | Digital supply pin (default function VDD_5); the pin table gives no voltage limit. |
| 12 | OSCIN | input | Default function OSCIN (high-speed crystal input); can be remapped to PD0 (see footnote 4 for EXTI restrictions, which apply to LQFP64/48 only). |
| 13 | OSCOUT | output | Default function OSCOUT (high-speed crystal output); can be remapped to PD1. |
| 14 | NRST | bidirectional | Default function NRST reset pin; the pin table gives no electrical limit. |
| 15 | PC0 | bidirectional | Default function PC0 with alternate ADC012_IN10. |
| 16 | PC1 | bidirectional | Default function PC1 with alternate ADC012_IN11. |
| 17 | PC2 | bidirectional | Default function PC2 with alternate ADC012_IN12. |
| 18 | PC3 | bidirectional | Default function PC3 with alternate ADC012_IN13. |
| 19 | VSSA | power_in | Analog ground pin (default function VSSA); the pin table gives no further limits. |
| 20 | VREF- | power_in | ADC reference voltage negative pin (default function VREF-); the pin table gives no voltage limit. |
| 21 | VREF+ | power_in | ADC reference voltage positive pin (default function VREF+); the pin table gives no voltage limit. |
| 22 | VDDA | power_in | Analog supply pin (default function VDDA); the pin table gives no voltage limit. |
| 23 | PA0-WKUP | bidirectional | Default function PA0 with WKUP wake-up and alternates USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI. |
| 24 | PA1 | bidirectional | Default function PA1 with alternates USART1_RTS, ADC012_IN1, TIMER1_CH1, TIMER4_CH1. |
| 25 | PA2 | bidirectional | Default function PA2 with alternates USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2, TIMER8_CH0 (footnote 3, VG/I/K devices), SPI0_IO2. |
| 26 | PA3 | bidirectional | Default function PA3 with alternates USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3, TIMER8_CH1 (footnote 3, VG/I/K devices), SPI0_IO3. |
| 27 | VSS_4 | power_in | Ground pin (default function VSS_4); the pin table gives no further limits. |
| 28 | VDD_4 | power_in | Digital supply pin (default function VDD_4); the pin table gives no voltage limit. |
| 29 | PA4 | bidirectional | Default function PA4 with alternates SPI0_NSS, USART1_CK, ADC01_IN4, DAC_OUT0; remap SPI2_NSS and I2S2_WS. |
| 30 | PA5 | bidirectional | Default function PA5 with alternates SPI0_SCK, ADC01_IN5, DAC_OUT1. |
| 31 | PA6 | bidirectional | Default function PA6 with alternates SPI0_MISO, ADC01_IN6, TIMER2_CH0, TIMER7_BRKIN, TIMER12_CH0 (footnote 3); remap TIMER0_BRKIN. |
| 32 | PA7 | bidirectional | Default function PA7 with alternates SPI0_MOSI, ADC01_IN7, TIMER2_CH1, TIMER7_CH0_ON, TIMER13_CH0 (footnote 3); remap TIMER0_CH0_ON. |
| 33 | PC4 | bidirectional | Default function PC4 with alternate ADC01_IN14. |
| 34 | PC5 | bidirectional | Default function PC5 with alternate ADC01_IN15. |
| 35 | PB0 | bidirectional | Default function PB0 with alternates ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON; remap TIMER0_CH1_ON. |
| 36 | PB1 | bidirectional | Default function PB1 with alternates ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON; remap TIMER0_CH2_ON. |
| 37 | PB2 | bidirectional | Default function PB2 (also BOOT1); 5 V tolerant (5VT) I/O. |
| 38 | PE7 | bidirectional | Default function PE7 with alternate EXMC_D4; remap TIMER0_ETI; 5 V tolerant (5VT) I/O. |
| 39 | PE8 | bidirectional | Default function PE8 with alternate EXMC_D5; remap TIMER0_CH0_ON; 5 V tolerant (5VT) I/O. |
| 40 | PE9 | bidirectional | Default function PE9 with alternate EXMC_D6; remap TIMER0_CH0; 5 V tolerant (5VT) I/O. |
| 41 | PE10 | bidirectional | Default function PE10 with alternate EXMC_D7; remap TIMER0_CH1_ON; 5 V tolerant (5VT) I/O. |
| 42 | PE11 | bidirectional | Default function PE11 with alternate EXMC_D8; remap TIMER0_CH1; 5 V tolerant (5VT) I/O. |
| 43 | PE12 | bidirectional | Default function PE12 with alternate EXMC_D9; remap TIMER0_CH2_ON; 5 V tolerant (5VT) I/O. |
| 44 | PE13 | bidirectional | Default function PE13 with alternate EXMC_D10; remap TIMER0_CH2; 5 V tolerant (5VT) I/O. |
| 45 | PE14 | bidirectional | Default function PE14 with alternate EXMC_D11; remap TIMER0_CH3; 5 V tolerant (5VT) I/O. |
| 46 | PE15 | bidirectional | Default function PE15 with alternate EXMC_D12; remap TIMER0_BRKIN; 5 V tolerant (5VT) I/O. |
| 47 | PB10 | bidirectional | Default function PB10 with alternates I2C1_SCL, USART2_TX; remap TIMER1_CH2; 5 V tolerant (5VT) I/O. |
| 48 | PB11 | bidirectional | Default function PB11 with alternates I2C1_SDA, USART2_RX; remap TIMER1_CH3; 5 V tolerant (5VT) I/O. |
| 49 | VSS_1 | power_in | Ground pin (default function VSS_1); the pin table gives no further limits. |
| 50 | VDD_1 | power_in | Digital supply pin (default function VDD_1); the pin table gives no voltage limit. |
| 51 | PB12 | bidirectional | Default function PB12 with alternates SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN, I2S1_WS; 5 V tolerant (5VT) I/O. |
| 52 | PB13 | bidirectional | Default function PB13 with alternates SPI1_SCK, USART2_CTS, TIMER0_CH0_ON, I2S1_CK; 5 V tolerant (5VT) I/O. |
| 53 | PB14 | bidirectional | Default function PB14 with alternates SPI1_MISO, USART2_RTS, TIMER0_CH1_ON, TIMER11_CH0 (footnote 3); 5 V tolerant (5VT) I/O. |
| 54 | PB15 | bidirectional | Default function PB15 with alternates SPI1_MOSI, TIMER0_CH2_ON, I2S1_SD, TIMER11_CH1 (footnote 3); 5 V tolerant (5VT) I/O. |
| 55 | PD8 | bidirectional | Default function PD8 with alternate EXMC_D13; remap USART2_TX; 5 V tolerant (5VT) I/O. |
| 56 | PD9 | bidirectional | Default function PD9 with alternate EXMC_D14; remap USART2_RX; 5 V tolerant (5VT) I/O. |
| 57 | PD10 | bidirectional | Default function PD10 with alternate EXMC_D15; remap USART2_CK; 5 V tolerant (5VT) I/O. |
| 58 | PD11 | bidirectional | Default function PD11 with alternate EXMC_A16; remap USART2_CTS; 5 V tolerant (5VT) I/O. |
| 59 | PD12 | bidirectional | Default function PD12 with alternate EXMC_A17; remap TIMER3_CH0, USART2_RTS; 5 V tolerant (5VT) I/O. |
| 60 | PD13 | bidirectional | Default function PD13 with alternate EXMC_A18; remap TIMER3_CH1; 5 V tolerant (5VT) I/O. |
| 61 | PD14 | bidirectional | Default function PD14 with alternate EXMC_D0; remap TIMER3_CH2; 5 V tolerant (5VT) I/O. |
| 62 | PD15 | bidirectional | Default function PD15 with alternate EXMC_D1; remap TIMER3_CH3, CTC_SYNC; 5 V tolerant (5VT) I/O. |
| 63 | PC6 | bidirectional | Default function PC6 with alternates I2S1_MCK, TIMER7_CH0, SDIO_D6; remap TIMER2_CH0; 5 V tolerant (5VT) I/O. |
| 64 | PC7 | bidirectional | Default function PC7 with alternates I2S2_MCK, TIMER7_CH1, SDIO_D7; remap TIMER2_CH1; 5 V tolerant (5VT) I/O. |
| 65 | PC8 | bidirectional | Default function PC8 with alternates TIMER7_CH2, SDIO_D0; remap TIMER2_CH2; 5 V tolerant (5VT) I/O. |
| 66 | PC9 | bidirectional | Default function PC9 with alternates TIMER7_CH3, SDIO_D1; remap TIMER2_CH3; 5 V tolerant (5VT) I/O. |
| 67 | PA8 | bidirectional | Default function PA8 with alternates USART0_CK, TIMER0_CH0, CK_OUT0, CTC_SYNC; 5 V tolerant (5VT) I/O. |
| 68 | PA9 | bidirectional | Default function PA9 with alternates USART0_TX, TIMER0_CH1; 5 V tolerant (5VT) I/O. |
| 69 | PA10 | bidirectional | Default function PA10 with alternates USART0_RX, TIMER0_CH2; 5 V tolerant (5VT) I/O. |
| 70 | PA11 | bidirectional | Default function PA11 with alternates USART0_CTS, CAN0_RX, USBDM, TIMER0_CH3; 5 V tolerant (5VT) I/O. |
| 71 | PA12 | bidirectional | Default function PA12 with alternates USART0_RTS, CAN0_TX, TIMER0_ETI, USBDP; 5 V tolerant (5VT) I/O. |
| 72 | PA13 | bidirectional | Default function JTMS/SWDIO; remap PA13; 5 V tolerant (5VT) I/O. |
| 73 | NC | unconnected | Not connected; no function is listed in the pin table. |
| 74 | VSS_2 | power_in | Ground pin (default function VSS_2); the pin table gives no further limits. |
| 75 | VDD_2 | power_in | Digital supply pin (default function VDD_2); the pin table gives no voltage limit. |
| 76 | PA14 | bidirectional | Default function JTCK/SWCLK; remap PA14; 5 V tolerant (5VT) I/O. |
| 77 | PA15 | bidirectional | Default function JTDI with alternates SPI2_NSS, I2S2_WS; remap TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS; 5 V tolerant (5VT) I/O. |
| 78 | PC10 | bidirectional | Default function PC10 with alternates UART3_TX, SDIO_D2; remap USART2_TX, SPI2_SCK, I2S2_CK; 5 V tolerant (5VT) I/O. |
| 79 | PC11 | bidirectional | Default function PC11 with alternates UART3_RX, SDIO_D3; remap USART2_RX, SPI2_MISO; 5 V tolerant (5VT) I/O. |
| 80 | PC12 | bidirectional | Default function PC12 with alternates UART4_TX, SDIO_CK; remap USART2_CK, SPI2_MOSI, I2S2_SD; 5 V tolerant (5VT) I/O. |
| 81 | PD0 | bidirectional | Default function PD0 with alternate EXMC_D2; remap CAN0_RX, OSCIN; 5 V tolerant (5VT) I/O. |
| 82 | PD1 | bidirectional | Default function PD1 with alternate EXMC_D3; remap CAN0_TX, OSCOUT; 5 V tolerant (5VT) I/O. |
| 83 | PD2 | bidirectional | Default function PD2 with alternates TIMER2_ETI, SDIO_CMD, UART4_RX; 5 V tolerant (5VT) I/O. |
| 84 | PD3 | bidirectional | Default function PD3 with alternate EXMC_CLK; remap USART1_CTS; 5 V tolerant (5VT) I/O. |
| 85 | PD4 | bidirectional | Default function PD4 with alternate EXMC_NOE; remap USART1_RTS; 5 V tolerant (5VT) I/O. |
| 86 | PD5 | bidirectional | Default function PD5 with alternate EXMC_NWE; remap USART1_TX; 5 V tolerant (5VT) I/O. |
| 87 | PD6 | bidirectional | Default function PD6 with alternate EXMC_NWAIT; remap USART1_RX; 5 V tolerant (5VT) I/O. |
| 88 | PD7 | bidirectional | Default function PD7 with alternates EXMC_NE0, EXMC_NCE1; remap USART1_CK; 5 V tolerant (5VT) I/O. |
| 89 | PB3 | bidirectional | Default function JTDO with alternates SPI2_SCK, I2S2_CK; remap PB3, TRACESWO, TIMER1_CH1, SPI0_SCK; 5 V tolerant (5VT) I/O. |
| 90 | PB4 | bidirectional | Default function NJTRST with alternate SPI2_MISO; remap TIMER2_CH0, PB4, SPI0_MISO; 5 V tolerant (5VT) I/O. |
| 91 | PB5 | bidirectional | Default function PB5 with alternates I2C0_SMBA, SPI2_MOSI, I2S2_SD; remap TIMER2_CH1, SPI0_MOSI; the pin table does not mark this pin as 5 V tolerant. |
| 92 | PB6 | bidirectional | Default function PB6 with alternates I2C0_SCL, TIMER3_CH0; remap USART0_TX, SPI0_IO2; 5 V tolerant (5VT) I/O. |
| 93 | PB7 | bidirectional | Default function PB7 with alternates I2C0_SDA, TIMER3_CH1, EXMC_NADV; remap USART0_RX, SPI0_IO3; 5 V tolerant (5VT) I/O. |
| 94 | BOOT0 | input | Boot mode selection input (default function BOOT0); the pin table gives no further limits. |
| 95 | PB8 | bidirectional | Default function PB8 with alternates TIMER3_CH2, SDIO_D4, TIMER9_CH0 (footnote 3); remap I2C0_SCL, CAN0_RX; 5 V tolerant (5VT) I/O. |
| 96 | PB9 | bidirectional | Default function PB9 with alternates TIMER3_CH3, SDIO_D5, TIMER10_CH0 (footnote 3); remap I2C0_SDA, CAN0_TX; 5 V tolerant (5VT) I/O. |
| 97 | PE0 | bidirectional | Default function PE0 with alternates TIMER3_ETI, EXMC_NBL0; 5 V tolerant (5VT) I/O. |
| 98 | PE1 | bidirectional | Default function PE1 with alternate EXMC_NBL1; 5 V tolerant (5VT) I/O. |
| 99 | VSS_3 | power_in | Ground pin (default function VSS_3); the pin table gives no further limits. |
| 100 | VDD_3 | power_in | Digital supply pin (default function VDD_3); the pin table gives no voltage limit. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External voltage range | VDD | -0.3 |  | 3.6 | V | Printed as VSS - 0.3 / VSS + 3.6 (referenced to VSS) | 51 |
| External analog supply voltage | VDDA | -0.3 |  | 3.6 | V | Printed as VSSA - 0.3 / VSSA + 3.6 (referenced to VSSA) | 51 |
| External battery supply voltage | VBAT | -0.3 |  | 3.6 | V | Printed as VSS - 0.3 / VSS + 3.6 (referenced to VSS) | 51 |
| Input voltage on 5V tolerant pin | VIN | -0.3 |  | 3.6 | V | Printed max as VDD + 3.6; VIN maximum cannot exceed 6.5 V | 51 |
| Input voltage on other I/O | VIN | -0.3 |  | 3.6 | V |  | 51 |
| Variations between different VDD power pins | /ΔVDDX/ |  |  | 50 | mV |  | 51 |
| Variations between different ground pins | /VSSX −VSS/ |  |  | 50 | mV |  | 51 |
| Maximum current for GPIO pins | IIO | -25 |  | 25 | mA |  | 51 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 51 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 51 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 51 |
| Electrostatic discharge voltage (human body model) | VESD(HBM) |  |  | 4000 | V | TA = 25 °C; JESD22-A114 | 62 |
| Electrostatic discharge voltage (charge device model) | VESD(CDM) |  |  | 800 | V | TA = 25 °C; JESD22-C101 | 62 |
| Static latch-up I-test | LU | -200 |  | 200 | mA | TA = 25 °C; JESD78 | 62 |
| Vsupply over voltage (latch-up) |  |  |  | 5.4 | V |  | 62 |
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V |  | 51 |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 51 |
| Battery supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 51 |
| AHB clock frequency | fHCLK |  |  | 120 | MHz |  | 52 |
| APB1 clock frequency | fAPB1 |  |  | 60 | MHz |  | 52 |
| APB2 clock frequency | fAPB2 |  |  | 120 | MHz |  | 52 |
| VDD rise time rate | tVDD | 0 |  |  | μs/V | Max printed as ∞ | 52 |
| VDD fall time rate | tVDD | 20 |  |  | μs/V | Max printed as ∞ | 52 |
| LVD hysteresis | VLVDhyst |  |  | 100 | mV | Guaranteed by design, not tested in production | 62 |
| Crystal or ceramic frequency (HXTAL) | fHXTAL | 4 | 8 | 32 | MHz | 2.6 V ≤ VDD ≤ 3.6 V | 63 |
| Recommended matching capacitance on OSCIN and OSCOUT | CHXTAL |  | 20 | 30 | pF |  | 63 |
| Crystal or ceramic duty cycle (HXTAL) | Ducy(HXTAL) | 30 | 50 | 70 | % |  | 63 |
| External clock source or oscillator frequency (HXTAL bypass) | fHXTAL_ext | 1 |  | 50 | MHz | VDD = 3.3 V | 63 |
| OSCIN high or low time | tH/L(HXTAL) | 5 |  |  | ns |  | 63 |
| OSCIN rise or fall time | tR/F(HXTAL) |  |  | 10 | ns |  | 63 |
| Crystal or ceramic duty cycle (LXTAL) | Ducy(LXTAL) | 30 |  | 70 | % |  | 64 |
| External clock source or oscillator frequency (LXTAL bypass) | fLXTAL_ext |  | 32.768 | 1000 | kHz | VDD = 3.3 V | 64 |
| OSC32IN high or low time | tH/L(LXTAL) | 450 |  |  | ns |  | 64 |
| OSC32IN rise or fall time | tR/F(LXTAL) |  |  | 50 | ns |  | 64 |
| IRC8M oscillator frequency accuracy, factory-trimmed | ACCIRC8M | -2.5 |  | 2.5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 65 |
| IRC8M oscillator duty cycle | DucyIRC8M | 45 | 50 | 55 | % | VDD = VDDA = 3.3 V | 65 |
| Low speed internal oscillator (IRC40K) frequency | fIRC40K | 20 | 40 | 45 | kHz | VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C | 65 |
| IRC48M oscillator frequency accuracy, factory-trimmed | ACCIRC48M | -4 |  | 5 | % | VDD = VDDA = 3.3 V, TA = -40°C ~ +85 °C | 66 |
| IRC48M oscillator duty cycle | DIRC48M | 45 | 50 | 55 | % | VDD = VDDA = 3.3 V | 66 |
| PLL input clock frequency | fPLLIN | 1 |  | 25 | MHz |  | 66 |
| PLL output clock frequency | fPLLOUT | 16 |  | 120 | MHz |  | 66 |
| PLL VCO output clock frequency | fVCO | 32 |  | 240 | MHz |  | 66 |
| PLL lock time | tLOCK |  |  | 300 | μs |  | 66 |
| Number of guaranteed program/erase cycles before failure (endurance) | PECYC | 100 |  |  | kcycles | TA = -40 °C ~ +85 °C | 67 |
| Word programming time | tPROG |  | 37.5 | 86 | μs | TA = -40°C ~ +85°C | 67 |
| Page erase time | tERASE |  | 45 | 200 | ms | TA = -40°C ~ +85°C; max with <50K cycles | 67 |
| Page erase time | tERASE |  |  | 300 | ms | TA = -40°C ~ +85°C; max with >50K & <100K cycles | 67 |
| Mass erase time (1MB) | tMERASE(1MB) |  | 6 | 28.8 | s | TA = -40°C ~ +85°C; max with <50K cycles | 67 |
| Mass erase time (1MB) | tMERASE(1MB) |  |  | 48 | s | TA = -40°C ~ +85°C; max with >50K & <100K cycles | 67 |
| NRST input low level voltage | VIL(NRST) | -0.5 |  |  | V | 2.6 V ≤ VDD = VDDA ≤ 3.6 V; printed max 0.3 VDD (not converted) | 67 |
| Low level output voltage for an IO pin (IIO = +8mA) | VOL |  |  | 0.16 | V | VDD = 3.3 V | 68 |
| Low level output voltage for an IO pin (IIO = +20mA) | VOL |  |  | 0.4 | V | VDD = 3.3 V | 68 |
| High level output voltage for an IO pin (IIO = +8mA) | VOH | 3.15 |  |  | V | VDD = 3.3 V | 68 |
| High level output voltage for an IO pin (IIO = +20mA) | VOH | 2.8 |  |  | V | VDD = 3.3 V | 68 |
| Internal pull-up resistor | RPU | 30 | 40 | 50 | kΩ | All pins, VIN = VSS | 68 |
| Internal pull-down resistor | RPD | 30 | 40 | 50 | kΩ | All pins, VIN = VDD | 68 |
| ADC clock | fADC | 0.1 |  | 40 | MHz |  | 70 |
| Sampling rate | fS | 0.007 |  | 2.86 | MSPS | 12-bit | 70 |

## CAD (KiCad official)

- Symbol: `GD32F303VGT6`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `gd32f303vgt6-etched.step` / `gd32f303vgt6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32f303vgt6.step` / `gd32f303vgt6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588893088404553728) (91 pp, sha256 `94da11f19fe397ec`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32f303vgt6-datasheet.pdf)