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GD32F303VBT6

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GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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GD32F303VBT6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F303VBT6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional Default PE2; alternate functions TRACECK and EXMC_A23; 5 V tolerant I/O.
2 PE3 bidirectional Default PE3; alternate functions TRACED0 and EXMC_A19; 5 V tolerant I/O.
3 PE4 bidirectional Default PE4; alternate functions TRACED1 and EXMC_A20; 5 V tolerant I/O.
4 PE5 bidirectional Default PE5; alternate functions TRACED2 and EXMC_A21; 5 V tolerant I/O.
5 PE6 bidirectional Default PE6; alternate functions TRACED3 and EXMC_A22; 5 V tolerant I/O.
6 VBAT power_in Backup power supply input (VBAT).
7 PC13-TAMPER-RTC bidirectional Default PC13; alternate function TAMPER-RTC.
8 PC14-OSC32IN bidirectional Default PC14; alternate function OSC32IN (low-speed crystal input).
9 PC15-OSC32OUT bidirectional Default PC15; alternate function OSC32OUT (low-speed crystal output).
10 VSS_5 power_in Digital ground.
11 VDD_5 power_in Digital supply voltage.
12 OSCIN input High-speed crystal oscillator input (OSCIN); remappable to PD0.
13 OSCOUT output High-speed crystal oscillator output (OSCOUT); remappable to PD1.
14 NRST bidirectional Default NRST reset pin.
15 PC0 bidirectional Default PC0; alternate function ADC012_IN10.
16 PC1 bidirectional Default PC1; alternate function ADC012_IN11.
17 PC2 bidirectional Default PC2; alternate function ADC012_IN12.
18 PC3 bidirectional Default PC3; alternate function ADC012_IN13.
19 VSSA power_in Analog ground.
20 VREF- power_in ADC reference voltage negative input.
21 VREF+ power_in ADC reference voltage positive input.
22 VDDA power_in Analog supply voltage.
23 PA0-WKUP bidirectional Default PA0; alternate functions WKUP, USART1_CTS, ADC012_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0 and TIMER7_ETI.
24 PA1 bidirectional Default PA1; alternate functions USART1_RTS, ADC012_IN1, TIMER1_CH1 and TIMER4_CH1.
25 PA2 bidirectional Default PA2; alternate functions USART1_TX, ADC012_IN2, TIMER1_CH2, TIMER4_CH2 and SPI0_IO2.
26 PA3 bidirectional Default PA3; alternate functions USART1_RX, ADC012_IN3, TIMER1_CH3, TIMER4_CH3 and SPI0_IO3.
27 VSS_4 power_in Digital ground.
28 VDD_4 power_in Digital supply voltage.
29 PA4 bidirectional Default PA4; alternate functions SPI0_NSS, USART1_CK, ADC01_IN4 and DAC_OUT0; remappable to SPI2_NSS and I2S2_WS.
30 PA5 bidirectional Default PA5; alternate functions SPI0_SCK, ADC01_IN5 and DAC_OUT1.
31 PA6 bidirectional Default PA6; alternate functions SPI0_MISO, ADC01_IN6, TIMER2_CH0 and TIMER7_BRKIN; remappable to TIMER0_BRKIN.
32 PA7 bidirectional Default PA7; alternate functions SPI0_MOSI, ADC01_IN7, TIMER2_CH1 and TIMER7_CH0_ON; remappable to TIMER0_CH0_ON.
33 PC4 bidirectional Default PC4; alternate function ADC01_IN14.
34 PC5 bidirectional Default PC5; alternate function ADC01_IN15.
35 PB0 bidirectional Default PB0; alternate functions ADC01_IN8, TIMER2_CH2 and TIMER7_CH1_ON; remappable to TIMER0_CH1_ON.
36 PB1 bidirectional Default PB1; alternate functions ADC01_IN9, TIMER2_CH3 and TIMER7_CH2_ON; remappable to TIMER0_CH2_ON.
37 PB2 bidirectional Default PB2 and BOOT1; 5 V tolerant I/O.
38 PE7 bidirectional Default PE7; alternate function EXMC_D4; remappable to TIMER0_ETI; 5 V tolerant I/O.
39 PE8 bidirectional Default PE8; alternate function EXMC_D5; remappable to TIMER0_CH0_ON; 5 V tolerant I/O.
40 PE9 bidirectional Default PE9; alternate function EXMC_D6; remappable to TIMER0_CH0; 5 V tolerant I/O.
41 PE10 bidirectional Default PE10; alternate function EXMC_D7; remappable to TIMER0_CH1_ON; 5 V tolerant I/O.
42 PE11 bidirectional Default PE11; alternate function EXMC_D8; remappable to TIMER0_CH1; 5 V tolerant I/O.
43 PE12 bidirectional Default PE12; alternate function EXMC_D9; remappable to TIMER0_CH2_ON; 5 V tolerant I/O.
44 PE13 bidirectional Default PE13; alternate function EXMC_D10; remappable to TIMER0_CH2; 5 V tolerant I/O.
45 PE14 bidirectional Default PE14; alternate function EXMC_D11; remappable to TIMER0_CH3; 5 V tolerant I/O.
46 PE15 bidirectional Default PE15; alternate function EXMC_D12; remappable to TIMER0_BRKIN; 5 V tolerant I/O.
47 PB10 bidirectional Default PB10; alternate functions I2C1_SCL and USART2_TX; remappable to TIMER1_CH2; 5 V tolerant I/O.
48 PB11 bidirectional Default PB11; alternate functions I2C1_SDA and USART2_RX; remappable to TIMER1_CH3; 5 V tolerant I/O.
49 VSS_1 power_in Digital ground.
50 VDD_1 power_in Digital supply voltage.
51 PB12 bidirectional Default PB12; alternate functions SPI1_NSS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN and I2S1_WS; 5 V tolerant I/O.
52 PB13 bidirectional Default PB13; alternate functions SPI1_SCK, USART2_CTS, TIMER0_CH0_ON and I2S1_CK; 5 V tolerant I/O.
53 PB14 bidirectional Default PB14; alternate functions SPI1_MISO, USART2_RTS and TIMER0_CH1_ON; 5 V tolerant I/O.
54 PB15 bidirectional Default PB15; alternate functions SPI1_MOSI, TIMER0_CH2_ON and I2S1_SD; 5 V tolerant I/O.
55 PD8 bidirectional Default PD8; alternate function EXMC_D13; remappable to USART2_TX; 5 V tolerant I/O.
56 PD9 bidirectional Default PD9; alternate function EXMC_D14; remappable to USART2_RX; 5 V tolerant I/O.
57 PD10 bidirectional Default PD10; alternate function EXMC_D15; remappable to USART2_CK; 5 V tolerant I/O.
58 PD11 bidirectional Default PD11; alternate function EXMC_A16; remappable to USART2_CTS; 5 V tolerant I/O.
59 PD12 bidirectional Default PD12; alternate function EXMC_A17; remappable to TIMER3_CH0 and USART2_RTS; 5 V tolerant I/O.
60 PD13 bidirectional Default PD13; alternate function EXMC_A18; remappable to TIMER3_CH1; 5 V tolerant I/O.
61 PD14 bidirectional Default PD14; alternate function EXMC_D0; remappable to TIMER3_CH2; 5 V tolerant I/O.
62 PD15 bidirectional Default PD15; alternate function EXMC_D1; remappable to TIMER3_CH3 and CTC_SYNC; 5 V tolerant I/O.
63 PC6 bidirectional Default PC6; alternate functions I2S1_MCK and TIMER7_CH0; remappable to TIMER2_CH0; 5 V tolerant I/O.
64 PC7 bidirectional Default PC7; alternate functions I2S2_MCK and TIMER7_CH1; remappable to TIMER2_CH1; 5 V tolerant I/O.
65 PC8 bidirectional Default PC8; alternate function TIMER7_CH2; remappable to TIMER2_CH2; 5 V tolerant I/O.
66 PC9 bidirectional Default PC9; alternate function TIMER7_CH3; remappable to TIMER2_CH3; 5 V tolerant I/O.
67 PA8 bidirectional Default PA8; alternate functions USART0_CK, TIMER0_CH0, CK_OUT0 and CTC_SYNC; 5 V tolerant I/O.
68 PA9 bidirectional Default PA9; alternate functions USART0_TX and TIMER0_CH1; 5 V tolerant I/O.
69 PA10 bidirectional Default PA10; alternate functions USART0_RX and TIMER0_CH2; 5 V tolerant I/O.
70 PA11 bidirectional Default PA11; alternate functions USART0_CTS, CAN0_RX, USBDM and TIMER0_CH3; 5 V tolerant I/O.
71 PA12 bidirectional Default PA12; alternate functions USART0_RTS, CAN0_TX, TIMER0_ETI and USBDP; 5 V tolerant I/O.
72 PA13 bidirectional Default JTMS/SWDIO; remappable to PA13 as GPIO; 5 V tolerant I/O.
73 NC unconnected Not connected.
74 VSS_2 power_in Digital ground.
75 VDD_2 power_in Digital supply voltage.
76 PA14 bidirectional Default JTCK/SWCLK; remappable to PA14 as GPIO; 5 V tolerant I/O.
77 PA15 bidirectional Default JTDI; alternate functions SPI2_NSS and I2S2_WS; remappable to TIMER1_CH0, TIMER1_ETI, PA15 and SPI0_NSS; 5 V tolerant I/O.
78 PC10 bidirectional Default PC10; alternate function UART3_TX; remappable to USART2_TX, SPI2_SCK and I2S2_CK; 5 V tolerant I/O.
79 PC11 bidirectional Default PC11; alternate function UART3_RX; remappable to USART2_RX and SPI2_MISO; 5 V tolerant I/O.
80 PC12 bidirectional Default PC12; alternate function UART4_TX; remappable to USART2_CK, SPI2_MOSI and I2S2_SD; 5 V tolerant I/O.
81 PD0 bidirectional Default PD0; alternate function EXMC_D2; remappable to CAN0_RX and OSCIN; 5 V tolerant I/O.
82 PD1 bidirectional Default PD1; alternate function EXMC_D3; remappable to CAN0_TX and OSCOUT; 5 V tolerant I/O.
83 PD2 bidirectional Default PD2; alternate functions TIMER2_ETI and UART4_RX; 5 V tolerant I/O.
84 PD3 bidirectional Default PD3; alternate function EXMC_CLK; remappable to USART1_CTS; 5 V tolerant I/O.
85 PD4 bidirectional Default PD4; alternate function EXMC_NOE; remappable to USART1_RTS; 5 V tolerant I/O.
86 PD5 bidirectional Default PD5; alternate function EXMC_NWE; remappable to USART1_TX; 5 V tolerant I/O.
87 PD6 bidirectional Default PD6; alternate function EXMC_NWAIT; remappable to USART1_RX; 5 V tolerant I/O.
88 PD7 bidirectional Default PD7; alternate functions EXMC_NE0 and EXMC_NCE1; remappable to USART1_CK; 5 V tolerant I/O.
89 PB3 bidirectional Default JTDO; alternate functions SPI2_SCK and I2S2_CK; remappable to PB3, TRACESWO, TIMER1_CH1 and SPI0_SCK; 5 V tolerant I/O.
90 PB4 bidirectional Default NJTRST; alternate function SPI2_MISO; remappable to TIMER2_CH0, PB4 and SPI0_MISO; 5 V tolerant I/O.
91 PB5 bidirectional Default PB5; alternate functions I2C0_SMBA, SPI2_MOSI and I2S2_SD; remappable to TIMER2_CH1 and SPI0_MOSI.
92 PB6 bidirectional Default PB6; alternate functions I2C0_SCL and TIMER3_CH0; remappable to USART0_TX and SPI0_IO2; 5 V tolerant I/O.
93 PB7 bidirectional Default PB7; alternate functions I2C0_SDA, TIMER3_CH1 and EXMC_NADV; remappable to USART0_RX and SPI0_IO3; 5 V tolerant I/O.
94 BOOT0 input Default BOOT0 boot mode selection input.
95 PB8 bidirectional Default PB8; alternate function TIMER3_CH2; remappable to I2C0_SCL and CAN0_RX; 5 V tolerant I/O.
96 PB9 bidirectional Default PB9; alternate function TIMER3_CH3; remappable to I2C0_SDA and CAN0_TX; 5 V tolerant I/O.
97 PE0 bidirectional Default PE0; alternate functions TIMER3_ETI and EXMC_NBL0; 5 V tolerant I/O.
98 PE1 bidirectional Default PE1; alternate function EXMC_NBL1; 5 V tolerant I/O.
99 VSS_3 power_in Digital ground.
100 VDD_3 power_in Digital supply voltage.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VDD External voltage range VDD -0.3 3.6 V Relative to VSS (printed VSS - 0.3 to VSS + 3.6) 52
VDDA External analog supply voltage VDDA -0.3 3.6 V Relative to VSSA (printed VSSA - 0.3 to VSSA + 3.6) 52
VBAT External battery supply voltage VBAT -0.3 3.6 V Relative to VSS (printed VSS - 0.3 to VSS + 3.6) 52
Input voltage on 5V tolerant pin VIN 3.6 V Printed as VDD + 3.6; VIN maximum value cannot exceed 5.5 V (note 3) 52
Input voltage on other I/O VIN -0.3 3.6 V Relative to VSS 52
Variations between different VDD power pins /ΔVDDX/ 50 mV 52
Variations between different ground pins /VSSX−VSS/ 50 mV 52
Maximum current for GPIO pins IIO -25 25 mA 52
Operating temperature range for grade 6 device TA -40 85 °C Grade 6 device 52
Power dissipation of LQFP100 PD 848 mW TA = 85°C, LQFP100 (grade 6 devices) 52
Storage temperature range TSTG -65 150 °C 52
Maximum junction temperature TJ 125 °C 52
Supply voltage VDD 2.6 3.3 3.6 V 53
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 53
Battery supply voltage VBAT 1.8 3.6 V 53
AHB clock frequency fHCLK 120 MHz 53
APB1 clock frequency fAPB1 60 MHz 53
APB2 clock frequency fAPB2 120 MHz 53
VDD rise time rate tVDD 0 μs/V 53
VDD fall time rate tVDD 20 μs/V 53
NRST Input low level voltage VIL(NRST) -0.3 V 2.6 V ≤ VDD = VDDA ≤ 3.6 V 69
NRST Input low level voltage (upper limit) VIL(NRST) 0.3 VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V; printed as 0.3 VDD 69
NRST Input high level voltage (lower limit) VIH(NRST) 0.7 VDD Printed as 0.7 VDD 69
NRST Input high level voltage (upper limit) VIH(NRST) 0.3 V Printed as VDD + 0.3 V 69
Standard IO low level input voltage VIL 0.3 VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V; printed as 0.3 VDD 70
5V-tolerant IO low level input voltage VIL 0.3 VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V; printed as 0.3 VDD 70
Standard IO high level input voltage (printed as low level) VIH 0.7 VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V; printed as 0.7 VDD 70
5V-tolerant IO high level input voltage (printed as low level) VIH 0.7 VDD 2.6 V ≤ VDD = VDDA ≤ 3.6 V; printed as 0.7 VDD 70
Low level output voltage for an IO pin VOL 0.17 V IIO = +8mA; VDD = 2.6 V 70
Low level output voltage for an IO pin VOL 0.16 V IIO = +8mA; VDD = 3.3 V 70
Low level output voltage for an IO pin VOL 0.15 V IIO = +8mA; VDD = 3.6 V 70
Low level output voltage for an IO pin VOL 0.49 V IIO = +20mA; VDD = 2.6 V 70
Low level output voltage for an IO pin VOL 0.4 V IIO = +20mA; VDD = 3.3 V 70
Low level output voltage for an IO pin VOL 0.34 V IIO = +20mA; VDD = 3.6 V 70
High level output voltage for an IO pin VOH 2.4 V IIO = +8mA; VDD = 2.6 V 70
High level output voltage for an IO pin VOH 3.15 V IIO = +8mA; VDD = 3.3 V 70
High level output voltage for an IO pin VOH 3.44 V IIO = +8mA; VDD = 3.6 V 70
High level output voltage for an IO pin VOH 2.02 V IIO = +20mA; VDD = 2.6 V 70
High level output voltage for an IO pin VOH 2.8 V IIO = +20mA; VDD = 3.3 V 70
Internal pull-up resistor RPU 30 40 50 kΩ All pins VIN = VSS 70
Internal pull-down resistor RPD 30 40 50 kΩ All pins VIN = VDD 70
High speed external crystal or ceramic frequency fHXTAL 4 8 32 MHz 2.6 V ≤ VDD ≤ 3.6 V 64
Crystal or ceramic duty cycle Ducy(HXTAL) 30 50 70 % 64
Recommended matching capacitance on OSCIN and OSCOUT CHXTAL 20 30 pF 64
External clock source or oscillator frequency (bypass) fHXTAL_ext 1 50 MHz VDD = 3.3 V 64
OSCIN input pin high level voltage (bypass) VHXTALH 0.7 VDD VDD = 3.3 V; printed as 0.7 VDD 64
OSCIN high or low time (bypass) tH/L(HXTAL) 5 ns 65
OSCIN rise or fall time (bypass) tR/F(HXTAL) 10 ns 65
IRC8M oscillator frequency accuracy, factory-trimmed (grade 6) ACCIRC8M -0.51 1.5 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C for grade 6 devices 66
IRC8M oscillator frequency accuracy, factory-trimmed (25 °C) ACCIRC8M -1 1 % VDD = VDDA = 3.3 V, TA = 25 °C 66
IRC8M oscillator duty cycle DucyIRC8M 45 50 55 % VDD = VDDA = 3.3 V 66
IRC48M oscillator frequency accuracy, factory-trimmed (grade 6) ACCIRC48M -1.42 1.3 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C for grade 6 devices 67
IRC48M oscillator frequency accuracy, factory-trimmed (25 °C) ACCIRC48M -2 2 % VDD = VDDA = 3.3 V, TA = 25 °C 67
PLL output clock frequency fPLLOUT 16 120 MHz 68
PLL lock time tLOCK 300 μs 68
Thermal resistance junction-to-ambient, LQFP100 θJA 47.19 °C/W Natural convection, 2S2P PCB 95
Thermal resistance junction-to-board, LQFP100 θJB 27.43 °C/W Cold plate, 2S2P PCB 96
Thermal resistance junction-to-case, LQFP100 θJC 8.57 °C/W Cold plate, 2S2P PCB 96

CAD (KiCad official)

  • Symbol: GD32F303VBT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: gd32f303vbt6-etched.step / gd32f303vbt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f303vbt6.step / gd32f303vbt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (101 pp, sha256 591b027012ddb77f, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF