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GD32F205VGT6

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GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-100(14x14). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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GD32F205VGT6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F205VGT6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PE2 bidirectional 5 V tolerant I/O; default function PE2, alternate functions TRACECK and EXMC_A23.
2 PE3 bidirectional 5 V tolerant I/O; default function PE3, alternate functions TRACED0 and EXMC_A19.
3 PE4 bidirectional 5 V tolerant I/O; default function PE4, alternate functions TRACED1 and EXMC_A20, remap LCD_B0.
4 PE5 bidirectional 5 V tolerant I/O; default function PE5, alternate functions TRACED2 and EXMC_A21, remap TM9_CH1 and LCD_G0.
5 PE6 bidirectional 5 V tolerant I/O; default function PE6, alternate functions TRACED3 and EXMC_A22, remap TM9_CH2 and LCD_G1.
6 VBAT power_in Default function VBAT; the pin definition table gives no further voltage limits for this pin.
7 PC13-TAMPER-RTC bidirectional Default function PC13; alternate functions TAMPER and RTC.
8 PC14-OSC32_IN bidirectional Default function PC14; alternate function OSC32_IN.
9 PC15-OSC32_OUT bidirectional Default function PC15; alternate function OSC32_OUT.
10 VSS_5 power_in Ground pin VSS_5; the pin definition table gives no further limits.
11 VDD_5 power_in Power pin VDD_5; the pin definition table gives no further limits.
12 PH0-OSC_IN input Default function OSC_IN (external oscillator input); remap functions PD0 and PH0.
13 PH1-OSC_OUT output Default function OSC_OUT (external oscillator output); remap functions PD1 and PH1.
14 NRST bidirectional Default function NRST (reset); the pin definition table gives no further limits.
15 PC0 bidirectional Default function PC0; alternate function ADC_IN10, remap EXMC_SDNWE.
16 PC1 bidirectional Default function PC1; alternate function ADC_IN11.
17 PC2 bidirectional Default function PC2; alternate function ADC_IN12, remap EXMC_SDNE0 and SPI2_MISO.
18 PC3 bidirectional Default function PC3; alternate function ADC_IN13, remap EXMC_SDCKE0, SPI2_MOSI and I2S2_SD.
19 VSSA power_in Analog ground pin VSSA; the pin definition table gives no further limits.
20 VREF- power_in Default function VREF-; the pin definition table gives no further limits.
21 VREF+ power_in Default function VREF+; the pin definition table gives no further limits.
22 VDDA power_in Analog supply pin VDDA; the block diagram shows the SAR ADC and DAC powered by VDDA.
23 PA0-WKUP bidirectional Default function PA0; alternate functions WKUP, USART2_CTS, ADC_IN0, TM2_CH1_ETR, TM5_CH1 and TM8_ETR, remap UART4_TX.
24 PA1 bidirectional Default function PA1; alternate functions USART2_RTS, ADC_IN1, TM2_CH2 and TM5_CH2, remap UART4_RX.
25 PA2 bidirectional Default function PA2; alternate functions USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3, TM9_CH1 and SPI1_IO3.
26 PA3 bidirectional Default function PA3; alternate functions USART2_RX, ADC_IN3, TM2_CH4, TM5_CH4, TM9_CH2 and SPI1_IO4, remap LCD_B5.
27 VSS_4 power_in Ground pin VSS_4; the pin definition table gives no further limits.
28 VDD_4 power_in Power pin VDD_4; the pin definition table gives no further limits.
29 PA4 bidirectional Default function PA4; alternate functions SPI1_NSS, USART2_CK, DAC_OUT1 and ADC12_IN4, remap SPI3_NSS, I2S3_WS and LCD_VSYNC.
30 PA5 bidirectional Default function PA5; alternate functions SPI1_SCK, ADC12_IN5 and DAC_OUT2, remap TM2_CH1_ETR and TM8_CH1N.
31 PA6 bidirectional Default function PA6; alternate functions SPI1_MISO, ADC12_IN6, TM3_CH1, TM8_BKIN and TM13_CH1, remap TM1_BKIN and LCD_G2.
32 PA7 bidirectional Default function PA7; alternate functions SPI1_MOSI, ADC12_IN7, TM3_CH2, TM8_CH1N and TM14_CH1, remap TM1_CH1N.
33 PC4 bidirectional Default function PC4; alternate function ADC12_IN14.
34 PC5 bidirectional Default function PC5; alternate function ADC12_IN15.
35 PB0 bidirectional Default function PB0; alternate functions ADC12_IN8, TM3_CH3 and TM8_CH2N, remap TM1_CH2N and LCD_R3.
36 PB1 bidirectional Default function PB1; alternate functions ADC12_IN9, TM3_CH4 and TM8_CH3N, remap TM1_CH3N and LCD_R6.
37 PB2 bidirectional 5 V tolerant I/O; default function PB2 with BOOT1 noted in the table.
38 PE7 bidirectional 5 V tolerant I/O; default function PE7, alternate functions EXMC_D4 and UART7_RX, remap TM1_ETR.
39 PE8 bidirectional 5 V tolerant I/O; default function PE8, alternate functions EXMC_D5 and UART7_TX, remap TM1_CH1N.
40 PE9 bidirectional 5 V tolerant I/O; default function PE9, alternate function EXMC_D6, remap TM1_CH1.
41 PE10 bidirectional 5 V tolerant I/O; default function PE10, alternate function EXMC_D7, remap TM1_CH2N.
42 PE11 bidirectional 5 V tolerant I/O; default function PE11, alternate function EXMC_D8, remap TM1_CH2 and LCD_G3.
43 PE12 bidirectional 5 V tolerant I/O; default function PE12, alternate function EXMC_D9, remap TM1_CH3N and LCD_B4.
44 PE13 bidirectional 5 V tolerant I/O; default function PE13, alternate function EXMC_D10, remap TM1_CH3 and LCD_DE.
45 PE14 bidirectional 5 V tolerant I/O; default function PE14, alternate function EXMC_D11, remap TM1_CH4 and LCD_CLK.
46 PE15 bidirectional 5 V tolerant I/O; default function PE15, alternate function EXMC_D12, remap TM1_BKIN and LCD_R7.
47 PB10 bidirectional 5 V tolerant I/O; default function PB10, alternate functions I2C2_SCL and USART3_TX, remap TM2_CH3, LCD_G4, SPI2_SCK and I2S2_CK.
48 PB11 bidirectional 5 V tolerant I/O; default function PB11, alternate functions I2C2_SDA and USART3_RX, remap TM2_CH4 and LCD_G5.
49 VSS_1 power_in Ground pin VSS_1; the pin definition table gives no further limits.
50 VDD_1 power_in Power pin VDD_1; the pin definition table gives no further limits.
51 PB12 bidirectional 5 V tolerant I/O; default function PB12, alternate functions SPI2_NSS, I2C2_SMBA, USART3_CK, TM1_BKIN, I2S2_WS and CAN2_RX.
52 PB13 bidirectional 5 V tolerant I/O; default function PB13, alternate functions SPI2_SCK, USART3_CTS, TM1_CH1N, I2S2_CK and CAN2_TX.
53 PB14 bidirectional 5 V tolerant I/O; default function PB14, alternate functions SPI2_MISO, USART3_RTS, TM1_CH2N and TM12_CH1.
54 PB15 bidirectional 5 V tolerant I/O; default function PB15, alternate functions SPI2_MOSI, TM1_CH3N, I2S2_SD and TM12_CH2.
55 PD8 bidirectional 5 V tolerant I/O; default function PD8, alternate function EXMC_D13, remap USART3_TX.
56 PD9 bidirectional 5 V tolerant I/O; default function PD9, alternate function EXMC_D14, remap USART3_RX.
57 PD10 bidirectional 5 V tolerant I/O; default function PD10, alternate function EXMC_D15, remap USART3_CK and LCD_B3.
58 PD11 bidirectional 5 V tolerant I/O; default function PD11, alternate function EXMC_A16, remap USART3_CTS.
59 PD12 bidirectional 5 V tolerant I/O; default function PD12, alternate function EXMC_A17, remap TM4_CH1 and USART3_RTS.
60 PD13 bidirectional 5 V tolerant I/O; default function PD13, alternate function EXMC_A18, remap TM4_CH2.
61 PD14 bidirectional 5 V tolerant I/O; default function PD14, alternate function EXMC_D0, remap TM4_CH3.
62 PD15 bidirectional 5 V tolerant I/O; default function PD15, alternate function EXMC_D1, remap TM4_CH4.
63 PC6 bidirectional 5 V tolerant I/O; default function PC6, alternate functions I2S2_MCK, TM8_CH1, SDIO_D6 and USART6_TX, remap TM3_CH1 and LCD_HSYNC.
64 PC7 bidirectional 5 V tolerant I/O; default function PC7, alternate functions I2S3_MCK, TM8_CH2, SDIO_D7 and USART6_RX, remap TM3_CH2 and LCD_G6.
65 PC8 bidirectional 5 V tolerant I/O; default function PC8, alternate functions TM8_CH3, SDIO_D0 and USART6_CK, remap TM3_CH3.
66 PC9 bidirectional 5 V tolerant I/O; default function PC9, alternate functions TM8_CH4, SDIO_D and MCO2, remap TM3_CH4 and I2C3_SDA.
67 PA8 bidirectional 5 V tolerant I/O; default function PA8, alternate functions USART1_CK, TM1_CH1, MCO, VCORE and OTG_FS_SOF, remap LCD_R6 and I2C3_SCL.
68 PA9 bidirectional 5 V tolerant I/O; default function PA9, alternate functions USART1_TX, TM1_CH2 and OTG_FS_VBUS, remap I2C3_SMBAI.
69 PA10 bidirectional 5 V tolerant I/O; default function PA10, alternate functions USART1_RX, TM1_CH3 and OTG_FS_ID.
70 PA11 bidirectional 5 V tolerant I/O; default function PA11, alternate functions USART1_CTS, CANRX, OTG_FS_DM, USBDM and TM1_CH4, remap LCD_R4.
71 PA12 bidirectional 5 V tolerant I/O; default function PA12, alternate functions USART1_RTS, OTG_FS_DP, CAN1_TX, TM1_ETR and USBDP, remap LCD_R5.
72 PA13 bidirectional 5 V tolerant I/O; default function JTMS/SWDIO, remap PA13.
73 NC unconnected Not connected; the pin definition table lists no function for this pin.
74 VSS_2 power_in Ground pin VSS_2; the pin definition table gives no further limits.
75 VDD_2 power_in Power pin VDD_2; the pin definition table gives no further limits.
76 PA14 bidirectional 5 V tolerant I/O; default function JTCK/SWCLK, remap PA14.
77 PA15 bidirectional 5 V tolerant I/O; default function JTDI, alternate functions SPI3_NSS and I2S3_WS, remap TM2_CH1_ETR, PA15 and SPI1_NSS.
78 PC10 bidirectional 5 V tolerant I/O; default function PC10, alternate functions UART4_TX and SDIO_D2, remap USART3_TX, SPI3_SCK, I2S3_CK and LCD_R2.
79 PC11 bidirectional 5 V tolerant I/O; default function PC11, alternate functions UART4_RX and SDIO_D3, remap USART3_RX and SPI3_MISO.
80 PC12 bidirectional 5 V tolerant I/O; default function PC12, alternate functions UART5_TX and SDIO_CK, remap USART3_CK, SPI3_MOSI and I2S3_SD.
81 PD0 bidirectional 5 V tolerant I/O; default function PD0, alternate function EXMC_D2, remap CAN1_RX and OSC_IN.
82 PD1 bidirectional 5 V tolerant I/O; default function PD1, alternate function EXMC_D3, remap CAN1_TX and OSC_OUT.
83 PD2 bidirectional 5 V tolerant I/O; default function PD2, alternate functions TM3_ETR, UART5_RX and SDIO_CMD.
84 PD3 bidirectional 5 V tolerant I/O; default function PD3, alternate function EXMC_CLK, remap USART2_CTS, LCD_G7, SPI2_SCK and I2S2_CK.
85 PD4 bidirectional 5 V tolerant I/O; default function PD4, alternate function EXMC_NOE, remap USART2_RTS.
86 PD5 bidirectional 5 V tolerant I/O; default function PD5, alternate function EXMC_NWE, remap USART2_TX.
87 PD6 bidirectional 5 V tolerant I/O; default function PD6, alternate function EXMC_NWAIT, remap USART2_RX, LCD_B2, SPI3_MOSI and I2S3_SD.
88 PD7 bidirectional 5 V tolerant I/O; default function PD7, alternate functions EXMC_NE1 and EXMC_NCE2, remap USART2_CK.
89 PB3 bidirectional 5 V tolerant I/O; default function JTDO, alternate functions SPI3_SCK and I2S3_CK, remap PB3, TRACESWO, TM2_CH2 and SPI1_SCK.
90 PB4 bidirectional 5 V tolerant I/O; default function NJTRST, alternate function SPI3_MISO, remap TM3_CH1, PB4 and SPI1_MISO.
91 PB5 bidirectional Default function PB5; alternate functions I2C1_SMBA, SPI3_MOSI and I2S3_SD, remap TM3_CH2, SPI1_MOSI, CAN2_RX and EXMC_SDCKE1.
92 PB6 bidirectional 5 V tolerant I/O; default function PB6, alternate functions I2C1_SCL and TM4_CH1, remap USART1_TX, CAN2_TX, EXMC_SDNE1 and SPI1_IO3.
93 PB7 bidirectional 5 V tolerant I/O; default function PB7, alternate functions I2C1_SDA, TM4_CH2 and EXMC_NADV, remap USART1_RX and SPI1_IO4.
94 BOOT0 input Input pin BOOT0 used for boot mode selection; the pin definition table gives no further limits.
95 PB8 bidirectional 5 V tolerant I/O; default function PB8, alternate functions TM4_CH3, TM10_CH1 and SDIO_D4, remap I2C1_SCL, CAN1_RX and LCD_B6.
96 PB9 bidirectional 5 V tolerant I/O; default function PB9, alternate functions TM4_CH4, TM11_CH1 and SDIO_D5, remap I2C1_SDA, CAN1_TX, LCD_B7, SPI2_NSS and I2S2_WS.
97 PE0 bidirectional 5 V tolerant I/O; default function PE0, alternate functions TM4_ETR, EXMC_NBL0 and UART8_RX.
98 PE1 bidirectional 5 V tolerant I/O; default function PE1, alternate functions EXMC_NBL1 and UART8_TX.
99 VSS_3 power_in Ground pin VSS_3; the pin definition table gives no further limits.
100 VDD_3 power_in Power pin VDD_3; the pin definition table gives no further limits.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package LQFP-100(14x14)
Category Embedded Processors & Controllers
Pins 100

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VDD external voltage range VDD -0.3 3.6 V 34
External analog supply voltage VDDA -0.3 3.6 V 34
External battery supply voltage VBAT -0.3 3.6 V 34
Input voltage on 5V tolerant pin VIN -0.3 4 V 5V tolerant pin; max printed as VDD + 4.0 34
Input voltage on other I/O VIN -0.3 4 V Other I/O 34
Maximum current for GPIO pins IIO 25 mA 34
Injected current on 5V tolerant pin IINJ -5 5 mA 5V tolerant pin 34
Injected current on other I/O IINJ -5 5 mA Other I/O 34
Injected current on all I/O ΣIINJ -25 25 mA 34
Operating temperature range TA -40 85 °C 34
Storage temperature range TSTG -55 150 °C 34
Maximum junction temperature TJ 125 °C 34
Supply voltage VDD 2.6 3.3 3.6 V 34
Analog supply voltage VDDA 2.6 3.3 3.6 V Same as VDD 34
Battery supply voltage VBAT 1.8 3.6 V 34
Power on reset threshold VPOR 2.32 2.4 2.48 V 36
Power down reset threshold VPDR 2.27 2.35 2.43 V 36
Electrostatic discharge voltage (human body model) VESD(HBM) 5000 V TA=25 °C; JESD22-A114 37
Electrostatic discharge voltage (charge device model) VESD(CDM) 500 V TA=25 °C; JESD22-C101 37
Static latch-up I-test LU -100 100 mA TA=25 °C; JESD78 37
Vsupply over voltage (latch-up) 5.4 V 37
High speed external oscillator (HSE) frequency fHSE 3 8 32 MHz VDD=3.3V 37
Recommended load capacitance on OSC_IN and OSC_OUT CHSE 20 30 pF 37
HSE oscillator duty cycle DHSE 48 50 52 % 37
Low speed external oscillator (LSE) frequency fLSE 32.768 1000 KHz VDD=VBAT=3.3V 38
Recommended load capacitance on OSC32_IN and OSC32_OUT CLSE 8 10 15 pF 38
LSE oscillator duty cycle DLSE 48 50 52 % 38
HSI oscillator frequency accuracy, factory-trimmed ACCHSI -2.5 1.5 % VDD=3.3V, TA=-40°C ~+105°C 38
HSI oscillator frequency accuracy, factory-trimmed ACCHSI -1.2 1.2 % VDD=3.3V, TA=0°C ~ +85°C 38
HSI oscillator frequency accuracy, factory-trimmed ACCHSI -1 1 % VDD=3.3V, TA=25°C 38
Low speed internal oscillator (LSI) frequency fLSI 30 40 60 KHz VDD=VBAT=3.3V, TA=-40°C ~ +85°C 38
LSI oscillator operating current IDDLSI 1 2 μA VDD=VBAT=3.3V, TA=25°C 38
LSI oscillator startup time tSULSI 80 μs VDD=VBAT=3.3V, TA=25°C 38
PLL input clock frequency fPLLIN 1 8 25 MHz 39
PLL output clock frequency fPLL 16 120 MHz 39
Number of guaranteed program/erase cycles before failure (endurance) PECYC 100 kcycles TA=-40°C ~ +85°C 39
Data retention time tRET 20 years TA=125°C 39
Word programming time tPROG 200 400 us TA=-40°C ~ +85°C 39
Page erase time tERASE 60 100 450 ms TA=-40°C ~ +85°C 39
Mass erase time tMERASE 3.2 9.6 s TA=-40°C ~ +85°C 39
Standard IO low level input voltage VIL -0.3 0.95 V VDD=2.6V 39
5V-tolerant IO low level input voltage VIL -0.3 0.9 V VDD=2.6V 39
Standard IO high level input voltage VIH 1.2 4 V VDD=2.6V 39
5V-tolerant IO high level input voltage VIH 1.5 5.5 V VDD=2.6V 39
Low level output voltage VOL 0.2 V VDD=2.6V 39
High level output voltage VOH 2.3 V VDD=2.6V 39
Internal pull-up resistor RPU 30 40 50 kΩ VIN=VSS 39
Internal pull-down resistor RPD 30 40 50 kΩ VIN=VDD 39
ADC clock frequency fADC 0.6 28 MHz 40
Sampling rate 12-bit fS 2 MHz 40
Input sampling switch resistance RADC 0.45 kΩ 40
ADC startup time tSU 1 μs 40
Load resistance RLOAD 5 kΩ Resistive load vs. VSSA with buffer ON 40
Load capacitance CLOAD 50 pF No pin/pad capacitance included 40
Differential non-linearity error DNE -3 3 LSB DAC in 12-bit 40
Integral non-linearity INL -4 4 LSB DAC in 12-bit 40
Offset error Offset -12 12 LSB DAC in 12-bit, VREF+ = 3.6 V 40
Gain error GE -0.5 0.5 % DAC in 12-bit 40
SCL clock frequency fSCL 0 100 KHz Standard mode 40
SCL clock frequency fSCL 0 400 KHz Fast mode 40

CAD (KiCad official)

  • Symbol: GD32F205VGT6
  • Footprint: Package_QFP:LQFP-100_14x14mm_P0.5mm
  • 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
  • 3D model files: gd32f205vgt6-etched.step / gd32f205vgt6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32f205vgt6.step / gd32f205vgt6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (45 pp, sha256 3675a96e84d6ec78, retrieved 2026-10-19, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF