# GD32F150C8T6

**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-48(7x7)

GD32F150C8T6 from GigaDevice Semicon Beijing, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup power supply pin with default function VBAT, as listed in the LQFP48 column of the pin definitions table. |
| 2 | PC13-TAMPER-RTC | bidirectional | I/O pin with default function PC13 and additional functions RTC_TAMP1, RTC_TS, RTC_OUT and WKUP2. |
| 3 | PC14-OSC32_IN | bidirectional | I/O pin with default function PC14 and additional function OSC32_IN for the low-speed 32.768 kHz oscillator input. |
| 4 | PC15-OSC32_OUT | bidirectional | I/O pin with default function PC15 and additional function OSC32_OUT for the low-speed 32.768 kHz oscillator output. |
| 5 | PF0-OSC_IN | bidirectional | 5 V tolerant I/O pin with default function PF0 and additional function OSC_IN for the high-speed external oscillator input. |
| 6 | PF1-OSC_OUT | bidirectional | 5 V tolerant I/O pin with default function PF1 and additional function OSC_OUT for the high-speed external oscillator output. |
| 7 | NRST | bidirectional | Reset pin with default function NRST as listed in the pin definitions table. |
| 8 | VSSA | power_in | Analog ground pin with default function VSSA. |
| 9 | VDDA | power_in | Analog supply pin with default function VDDA. |
| 10 | PA0-WKUP | bidirectional | I/O pin with default function PA0; alternate functions include USART1_CTS, USART2_CTS, TM2_CH1_ETR, CMP1_OUT, TSI_G1_IO1 and I2C2_SCL, and additional functions ADC_IN0, CMP1_INM6, RTC_TAMP2 and WKUP1. |
| 11 | PA1 | bidirectional | I/O pin with default function PA1; alternate functions include USART1_RTS, USART2_RTS, TM2_CH2, TSI_G1_IO2, I2C2_SDA and EVENTOUT, and additional functions ADC_IN1 and CMP1_INP. |
| 12 | PA2 | bidirectional | I/O pin with default function PA2; alternate functions include USART1_TX, USART2_TX, TM2_CH3, TM15_CH1, CMP2_OUT and TSI_G1_IO3, and additional functions ADC_IN2 and CMP2_INM6. |
| 13 | PA3 | bidirectional | I/O pin with default function PA3; alternate functions include USART1_RX, USART2_RX, TM2_CH4, TM15_CH2 and TSI_G1_IO4, and additional functions ADC_IN3 and CMP2_INP. |
| 14 | PA4 | bidirectional | I/O pin with default function PA4; alternate functions include SPI1_NSS, I2S1_WS, USART1_RX, USART2_RX, TM14_CH1, TSI_G2_IO1 and SPI2_NSS, and additional functions ADC_IN4, CMP1_INM4, CMP2_INM4 and DAC1_OUT. |
| 15 | PA5 | bidirectional | I/O pin with default function PA5; alternate functions include SPI1_SCK, I2S1_CK, CEC, TM2_CH1_ETR and TSI_G2_IO2, and additional functions ADC_IN5, CMP1_INM5 and CMP2_INM5. |
| 16 | PA6 | bidirectional | I/O pin with default function PA6; alternate functions include SPI1_MISO, I2S1_MCK, TM3_CH1, TM1_BKIN, TM16_CH1, CMP1_OUT, TSI_G2_IO3 and EVENTOUT, and additional function ADC_IN6. |
| 17 | PA7 | bidirectional | I/O pin with default function PA7; alternate functions include SPI1_MOSI, I2S1_SD, TM3_CH2, TM14_CH1, TM1_CH1N, TM17_CH1, CMP2_OUT, TSI_G2_IO4 and EVENTOUT, and additional function ADC_IN7. |
| 18 | PB0 | bidirectional | I/O pin with default function PB0; alternate functions include TM3_CH3, TM1_CH2N, TSI_G3_IO2, USART2_RX and EVENTOUT, and additional function ADC_IN8. |
| 19 | PB1 | bidirectional | I/O pin with default function PB1; alternate functions include TM3_CH4, TM14_CH1, TM1_CH3N, TSI_G3_IO3 and SPI2_SCK, and additional function ADC_IN9. |
| 20 | PB2 | bidirectional | 5 V tolerant I/O pin with default function PB2; alternate function TSI_G3_IO4 is listed. |
| 21 | PB10 | bidirectional | 5 V tolerant I/O pin with default function PB10; alternate functions include I2C2_SCL, CEC, TM2_CH3 and TSI_SYNC. |
| 22 | PB11 | bidirectional | 5 V tolerant I/O pin with default function PB11; alternate functions include I2C2_SDA, TM2_CH4, TSI_G6_IO1 and EVENTOUT. |
| 23 | VSS | power_in | Digital ground pin with default function VSS. |
| 24 | VDD | power_in | Digital supply pin with default function VDD. |
| 25 | PB12 | bidirectional | 5 V tolerant I/O pin with default function PB12; alternate functions include SPI1_NSS, SPI2_NSS, TM1_BKIN, TSI_G6_IO2, I2C2_SMBA and EVENTOUT. |
| 26 | PB13 | bidirectional | 5 V tolerant I/O pin with default function PB13; alternate functions include SPI1_SCK, SPI2_SCK, TM1_CH1N and TSI_G6_IO3. |
| 27 | PB14 | bidirectional | 5 V tolerant I/O pin with default function PB14; alternate functions include SPI1_MISO, SPI2_MISO, TM1_CH2N, TM15_CH1 and TSI_G6_IO4. |
| 28 | PB15 | bidirectional | 5 V tolerant I/O pin with default function PB15; alternate functions include SPI1_MOSI, SPI2_MOSI, TIM1_CH3N, TM15_CH1N and TM15_CH2, and additional function RTC_REFIN. |
| 29 | PA8 | bidirectional | 5 V tolerant I/O pin with default function PA8; alternate functions include USART1_CK, TM1_CH1, MCO, USART2_TX and EVENTOUT. |
| 30 | PA9 | bidirectional | 5 V tolerant I/O pin with default function PA9; alternate functions include USART1_TX, TM1_CH2, TM15_BKIN, TSI_G4_IO1 and I2C1_SCL. |
| 31 | PA10 | bidirectional | 5 V tolerant I/O pin with default function PA10; alternate functions include USART1_RX, TM1_CH3, TM17_BKIN, TSI_G4_IO2 and I2C1_SDA. |
| 32 | PA11 | bidirectional | 5 V tolerant I/O pin with default function PA11; alternate functions include USART1_CTS, TM1_CH4, CMP1_OUT, TSI_G4_IO3 and EVENTOUT, and additional function USBDM. |
| 33 | PA12 | bidirectional | 5 V tolerant I/O pin with default function PA12; alternate functions include USART1_RTS, TM1_ETR, CMP2_OUT, TSI_G4_IO4 and EVENTOUT, and additional function USBDP. |
| 34 | PA13 | bidirectional | 5 V tolerant I/O pin with default function PA13; alternate functions include IR_OUT, SWDAT and SPI2_MISO. |
| 35 | PF6 | bidirectional | 5 V tolerant I/O pin with default function PF6; the table lists I2C2_SCL as its alternate function. |
| 36 | PF7 | bidirectional | 5 V tolerant I/O pin with default function PF7; the table lists I2C2_SDA as its alternate function. |
| 37 | PA14 | bidirectional | 5 V tolerant I/O pin with default function PA14; alternate functions include USART1_TX, USART2_TX, SWCLK and SPI2_MOSI. |
| 38 | PA15 | bidirectional | 5 V tolerant I/O pin with default function PA15; alternate functions include SPI1_NSS, I2S1_WS, USART1_RX, USART2_RX, TM2_CH1_ETR, SPI2_NSS and EVENTOUT. |
| 39 | PB3 | bidirectional | 5 V tolerant I/O pin with default function PB3; alternate functions include SPI1_SCK/I2S1_CK, TM2_CH2, TSI_G5_IO1 and EVENTOUT. |
| 40 | PB4 | bidirectional | 5 V tolerant I/O pin with default function PB4; alternate functions include SPI1_MISO/I2S1_MCK, TM3_CH1, TSI_G5_IO2 and EVENTOUT. |
| 41 | PB5 | bidirectional | 5 V tolerant I/O pin with default function PB5; alternate functions include SPI1_MOSI/I2S1_SD, I2C1_SMBA, TM16_BKIN and TM3_CH2. |
| 42 | PB6 | bidirectional | 5 V tolerant I/O pin with default function PB6; alternate functions include I2C1_SCL, USART1_TX, TM16_CH1N and TSI_G5_IO3. |
| 43 | PB7 | bidirectional | 5 V tolerant I/O pin with default function PB7; alternate functions include I2C1_SDA, USART1_RX, TM17_CH1N and TSI_G5_IO4. |
| 44 | BOOT0 | input | Boot mode selection input with default function BOOT0. |
| 45 | PB8 | bidirectional | 5 V tolerant I/O pin with default function PB8; alternate functions include I2C1_SCL, CEC, TM16_CH1 and TSI_SYNC. |
| 46 | PB9 | bidirectional | 5 V tolerant I/O pin with default function PB9; alternate functions include I2C1_SDA, IR_OUT, TM17_CH1 and EVENTOUT. |
| 47 | VSS | power_in | Digital ground pin with default function VSS. |
| 48 | VDD | power_in | Digital supply pin with default function VDD. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-48(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 48 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Maximum current for GPIO pins | IIO |  |  | 25 | mA |  | 28 |
| Input voltage on other I/O | VIN |  |  | 4 | V |  | 28 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 28 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 28 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 28 |
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V |  | 28 |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 28 |
| Battery supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 28 |
| Power on reset threshold | VPOR | 2.32 | 2.4 | 2.48 | V | PDR_S=0 | 30 |
| Power down reset threshold | VPDR | 2.27 | 2.35 | 2.43 | V | PDR_S=0 | 30 |
| Power down reset threshold | VPDR | 1.72 | 1.8 | 1.88 | V | PDR_S=1 | 30 |
| Electrostatic discharge voltage (human body model) | VESD(HBM) |  |  | 5000 | V | TA=25 °C; JESD22-A114 | 31 |
| Static latch-up I-test | LU | -100 |  | 100 | mA | TA=25 °C; JESD78 | 31 |
| High Speed External oscillator (HSE) frequency | fHSE | 4 | 8 | 32 | MHz | VDD=3.3V | 31 |
| Recommended load capacitance on OSC_IN and OSC_OUT | CHSE |  | 20 | 30 | pF |  | 31 |
| Low Speed External oscillator (LSE) frequency | fLSE |  | 32.768 | 1000 | KHz | VDD=VBAT=3.3V | 32 |
| Recommended load capacitance on OSC32_IN and OSC32_OUT | CLSE |  |  | 15 | pF |  | 32 |
| HSI oscillator Frequency accuracy, Factory-trimmed | ACCHSI | -2.5 |  | 1.5 | % | VDD=3.3V, TA=-40°C ~+105°C | 32 |
| HSI oscillator Frequency accuracy, Factory-trimmed | ACCHSI | -1.2 |  | 1.2 | % | VDD=3.3V, TA=0°C ~ +85°C | 32 |
| HSI oscillator Frequency accuracy, Factory-trimmed | ACCHSI | -1 |  | 1 | % | VDD=3.3V, TA=25°C | 32 |
| HSI oscillator operating current | IDDHSI |  | 80 | 100 | μA | VDD=3.3V, fHSI=8MHz | 32 |
| Low Speed Internal oscillator (LSI) frequency | fLSI | 30 | 40 | 60 | KHz | VDD=VBAT=3.3V, TA=-40°C ~ +85°C | 32 |
| LSI oscillator operating current | IDDLSI |  | 1 | 2 | μA | VDD=VBAT=3.3V, TA=25°C | 32 |
| PLL input clock frequency | fPLLIN | 1 | 8 | 25 | MHz |  | 33 |
| PLL output clock frequency | fPLL | 16 |  | 72 | MHz |  | 33 |
| PLL lock time | tLOCK |  |  | 200 | μs |  | 33 |
| Number of guaranteed program/erase cycles before failure (Endurance) | PECYC | 100 |  |  | kcycles | TA=-40°C ~ +85°C | 33 |
| Data retention time | tRET | 20 |  |  | years | TA=125°C | 33 |
| Word programming time | tPROG | 200 |  | 400 | us | TA=-40°C ~ +85°C | 33 |
| Page erase time | tERASE | 60 | 100 | 450 | ms | TA=-40°C ~ +85°C | 33 |
| Standard IO Low level input voltage | VIL | -0.3 |  | 0.95 | V | VDD=2.6V | 33 |
| 5V-tolerant IO Low level input voltage | VIL | -0.3 |  | 0.9 | V | VDD=2.6V | 33 |
| Standard IO High level input voltage | VIH | 1.2 |  | 4 | V | VDD=2.6V | 33 |
| 5V-tolerant IO High level input voltage | VIH | 1.5 |  | 5.5 | V | VDD=2.6V | 33 |
| Low level output voltage | VOL |  |  | 0.2 | V | VDD=2.6V | 33 |
| High level output voltage | VOH | 2.3 |  |  | V | VDD=2.6V | 33 |
| Internal pull-up resistor | RPU | 30 | 40 | 50 | kΩ | VIN=VSS | 33 |
| ADC clock | fADC | 0.6 |  | 14 | MHz |  | 34 |
| Sampling rate | fS |  |  | 1 | MHz |  | 34 |
| ADC conversion time | fADCCONV | 1 |  | 18 | μs | fADC=14MHz | 34 |
| Load resistance | RLOAD | 5 |  |  | kΩ | Resistive load vs. VSSA with buffer ON | 34 |
| Load capacitance | CLOAD |  |  | 50 | pF | No pin/pad capacitance included | 34 |
| Differential non-linearity error | DNE | -3 |  | 3 | LSB | DAC in 12-bit | 34 |
| Integral non-linearity | INL | -4 |  | 4 | LSB | DAC in 12-bit | 34 |
| Offset error | Offset | -12 |  | 12 | LSB | DAC in 12-bit, VREF+ = 3.6 V | 34 |
| Gain error | GE | -0.5 |  | 0.5 | % | DAC in 12-bit | 34 |
| SCL clock frequency (Standard mode) | fSCL | 0 |  | 100 | KHz |  | 34 |
| SCL clock frequency (Fast mode) | fSCL | 0 |  | 400 | KHz |  | 34 |
| SCL clock high time (Standard mode) | tSCL(H) | 4 |  |  | ns |  | 34 |
| SCL clock high time (Fast mode) | tSCL(H) | 0.6 |  |  | ns |  | 34 |
| SCL clock low time (Standard mode) | tSCL(L) | 4.7 |  |  | ns |  | 34 |
| SCL clock low time (Fast mode) | tSCL(L) | 1.3 |  |  | ns |  | 34 |
| SCK clock frequency | fSCK |  |  | 18 | MHz |  | 35 |
| Data output valid time (SPI master mode) | tV(MO) |  |  | 25 | ns |  | 35 |
| Data input setup time (SPI master mode) | tSU(MI) | 5 |  |  | ns |  | 35 |
| Data input hold time (SPI master mode) | tH(MI) | 5 |  |  | ns |  | 35 |
| NSS enable setup time (SPI slave mode) | tSU(NSS) | 74 |  |  | ns | fPCLK=54MHz | 35 |
| Data output access time (SPI slave mode) | tA(SO) | 0 |  | 55 | ns | fPCLK=54MHz | 35 |
| Data output valid time (SPI slave mode) | tV(SO) |  |  | 25 | ns |  | 35 |

## CAD (KiCad official)

- Symbol: `GD32F150C8T6`
- Footprint: `Package_QFP:LQFP-48_7x7mm_P0.5mm`
- 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
- 3D model files: `gd32f150c8t6-etched.step` / `gd32f150c8t6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32f150c8t6.step` / `gd32f150c8t6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175870919200768) (41 pp, sha256 `9832519f8cc8bcc9`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32f150c8t6-datasheet.pdf)