# GD32F107VCT6

**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-100(14x14)

GD32F107VCT6 from GigaDevice Semicon Beijing, in a LQFP-100(14x14). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | PE2 | bidirectional | 5 V tolerant I/O with default function PE2 and alternates TRACECK and EXMC_A23. |
| 2 | PE3 | bidirectional | 5 V tolerant I/O with default function PE3 and alternates TRACED0 and EXMC_A19. |
| 3 | PE4 | bidirectional | 5 V tolerant I/O with default function PE4 and alternates TRACED1 and EXMC_A20. |
| 4 | PE5 | bidirectional | 5 V tolerant I/O with default function PE5 and alternates TRACED2 and EXMC_A21; the TM9_CH1 remap is footnoted for GD32F107xF/xG only. |
| 5 | PE6 | bidirectional | 5 V tolerant I/O with default function PE6 and alternates TRACED3 and EXMC_A22; the TM9_CH2 remap is footnoted for GD32F107xF/xG only. |
| 6 | VBAT | power_in | Power supply pin VBAT; the pin table gives no voltage limit for it. |
| 7 | PC13-TAMPER-RTC | bidirectional | I/O with default function PC13 and alternate TAMPER-RTC; no 5 V tolerance is listed. |
| 8 | PC14-OSC32_IN | bidirectional | I/O with default function PC14 and alternate OSC32_IN; no 5 V tolerance is listed. |
| 9 | PC15-OSC32_OUT | bidirectional | I/O with default function PC15 and alternate OSC32_OUT; no 5 V tolerance is listed. |
| 10 | VSS_5 | power_in | Ground pin VSS_5. |
| 11 | VDD_5 | power_in | Power supply pin VDD_5. |
| 12 | OSC_IN | input | Default function OSC_IN; remap to PD0 is footnoted for GD32F107xF/xG only. |
| 13 | OSC_OUT | output | Default function OSC_OUT; remap to PD1 is footnoted for GD32F107xF/xG only. |
| 14 | NRST | bidirectional | Default function NRST, listed as an I/O pin with no level specified. |
| 15 | PC0 | bidirectional | I/O with default function PC0 and alternate ADC_IN10. |
| 16 | PC1 | bidirectional | I/O with default function PC1 and alternates ADC_IN11, ETH_MII_MDC and ETH_RMII_MDC. |
| 17 | PC2 | bidirectional | I/O with default function PC2 and alternates ADC_IN12 and ETH_MII_TXD2. |
| 18 | PC3 | bidirectional | I/O with default function PC3 and alternates ADC_IN13 and ETH_MII_TX_CLK. |
| 19 | VSSA | power_in | Analog ground pin VSSA. |
| 20 | VREF- | power_in | Reference voltage pin VREF- (name as printed in the datasheet). |
| 21 | VREF+ | power_in | Reference voltage pin VREF+. |
| 22 | VDDA | power_in | Analog supply pin VDDA. |
| 23 | PA0-WKUP | bidirectional | I/O with default function PA0 and alternates WKUP, USART2_CTS, ADC_IN0, TM2_CH1_ETR, TM5_CH1, TM8_ETR and ETH_MII_CRS_WKUP. |
| 24 | PA1 | bidirectional | I/O with default function PA1 and alternates USART2_RTS, ADC_IN1, TM2_CH2, TM5_CH2, ETH_MII_RX_CLK and ETH_RMII_REF_CLK. |
| 25 | PA2 | bidirectional | I/O with default function PA2 and alternates USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3, ETH_MII_MDIO and ETH_RMII_MDIO; the TM9_CH1 remap is footnoted for GD32F107xF/xG only. |
| 26 | PA3 | bidirectional | I/O with default function PA3 and alternates USART2_RX, ADC_IN3, TM2_CH4, TM5_CH4 and ETH_MII_COL. |
| 27 | VSS_4 | power_in | Ground pin VSS_4. |
| 28 | VDD_4 | power_in | Power supply pin VDD_4. |
| 29 | PA4 | bidirectional | I/O with default function PA4 and alternates SPI1_NSS, USART2_CK, ADC12_IN4 and DAC_OUT1. |
| 30 | PA5 | bidirectional | I/O with default function PA5 and alternates SPI1_SCK, ADC12_IN5 and DAC_OUT2. |
| 31 | PA6 | bidirectional | I/O with default function PA6 and alternates SPI1_MISO, ADC12_IN6, TM3_CH1 and TM8_BKIN; the TM13_CH1 function is footnoted for GD32F107xF/xG only. |
| 32 | PA7 | bidirectional | I/O with default function PA7 and alternates SPI1_MOSI, ADC12_IN7, TM3_CH2, TM8_CH1N, ETH_MII_RX_DV and ETH_RMII_CRS_DV; the TM14_CH1 function is footnoted for GD32F107xF/xG only. |
| 33 | PC4 | bidirectional | I/O with default function PC4 and alternates ADC12_IN14, ETH_MII_RXD0 and ETH_RMII_RXD0. |
| 34 | PC5 | bidirectional | I/O with default function PC5 and alternates ADC12_IN15, ETH_MII_RXD1 and ETH_RMII_RXD1. |
| 35 | PB0 | bidirectional | I/O with default function PB0 and alternates ADC12_IN8, TM3_CH3, TM8_CH2N and ETH_MII_RXD2. |
| 36 | PB1 | bidirectional | I/O with default function PB1 and alternates ADC12_IN9, TM3_CH4, TM8_CH3N and ETH_MII_RXD3. |
| 37 | PB2 | bidirectional | 5 V tolerant I/O with default function PB2/BOOT1. |
| 38 | PE7 | bidirectional | 5 V tolerant I/O with default function PE7, alternate EXMC_D4 and remap TM1_ETR. |
| 39 | PE8 | bidirectional | 5 V tolerant I/O with default function PE8, alternate EXMC_D5 and remap TM1_CH1N. |
| 40 | PE9 | bidirectional | 5 V tolerant I/O with default function PE9, alternate EXMC_D6 and remap TM1_CH1. |
| 41 | PE10 | bidirectional | 5 V tolerant I/O with default function PE10, alternate EXMC_D7 and remap TM1_CH2N. |
| 42 | PE11 | bidirectional | 5 V tolerant I/O with default function PE11, alternate EXMC_D8 and remap TM1_CH2. |
| 43 | PE12 | bidirectional | 5 V tolerant I/O with default function PE12, alternate EXMC_D9 and remap TM1_CH3N. |
| 44 | PE13 | bidirectional | 5 V tolerant I/O with default function PE13, alternate EXMC_D10 and remap TM1_CH3. |
| 45 | PE14 | bidirectional | 5 V tolerant I/O with default function PE14, alternate EXMC_D11 and remap TM1_CH4. |
| 46 | PE15 | bidirectional | 5 V tolerant I/O with default function PE15, alternate EXMC_D12 and remap TM1_BKIN. |
| 47 | PB10 | bidirectional | 5 V tolerant I/O with default function PB10, alternates I2C2_SCL, USART3_TX and ETH_MII_RX_ER, and remap TM2_CH3. |
| 48 | PB11 | bidirectional | 5 V tolerant I/O with default function PB11, alternates I2C2_SDA, USART3_RX, ETH_MII_TX_EN and ETH_RMII_TX_EN, and remap TM2_CH4. |
| 49 | VSS_1 | power_in | Ground pin VSS_1. |
| 50 | VDD_1 | power_in | Power supply pin VDD_1. |
| 51 | PB12 | bidirectional | 5 V tolerant I/O with default function PB12 and alternates SPI2_NSS, I2C2_SMBAI, USART3_CK, TM1_BKIN, I2S2_WS, CAN2_RX, ETH_MII_TXD0 and ETH_RMII_TXD0. |
| 52 | PB13 | bidirectional | 5 V tolerant I/O with default function PB13 and alternates SPI2_SCK, USART3_CTS, TM1_CH1N, I2S2_CK, CAN2_TX, ETH_MII_TXD1 and ETH_RMII_TXD1. |
| 53 | PB14 | bidirectional | 5 V tolerant I/O with default function PB14 and alternates SPI2_MISO, USART3_RTS and TM1_CH2N; the TM12_CH1 function is footnoted for GD32F107xF/xG only. |
| 54 | PB15 | bidirectional | 5 V tolerant I/O with default function PB15 and alternates SPI2_MOSI, TM1_CH3N and I2S2_SD; the TM12_CH2 function is footnoted for GD32F107xF/xG only. |
| 55 | PD8 | bidirectional | 5 V tolerant I/O with default function PD8, alternate EXMC_D13 and remaps USART3_TX, ETH_MII_RX_DV and ETH_RMII_CRS_DV. |
| 56 | PD9 | bidirectional | 5 V tolerant I/O with default function PD9, alternate EXMC_D14 and remaps USART3_RX, ETH_MII_RXD0 and ETH_RMII_RXD0. |
| 57 | PD10 | bidirectional | 5 V tolerant I/O with default function PD10, alternate EXMC_D15 and remaps USART3_CK, ETH_MII_RXD1 and ETH_RMII_RXD1. |
| 58 | PD11 | bidirectional | 5 V tolerant I/O with default function PD11, alternate EXMC_A16 and remaps USART3_CTS and ETH_MII_RXD2. |
| 59 | PD12 | bidirectional | 5 V tolerant I/O with default function PD12, alternate EXMC_A17 and remaps TM4_CH1 and USART3_RTS. |
| 60 | PD13 | bidirectional | 5 V tolerant I/O with default function PD13, alternate EXMC_A18 and remaps TM4_CH2, USART3_RTS and ETH_MII_RXD3. |
| 61 | PD14 | bidirectional | 5 V tolerant I/O with default function PD14, alternate EXMC_D0 and remap TM4_CH3. |
| 62 | PD15 | bidirectional | 5 V tolerant I/O with default function PD15, alternate EXMC_D1 and remap TM4_CH4. |
| 63 | PC6 | bidirectional | 5 V tolerant I/O with default function PC6, alternates I2S2_MCK and TM8_CH1, and remap TM3_CH1. |
| 64 | PC7 | bidirectional | 5 V tolerant I/O with default function PC7, alternates I2S3_MCK and TM8_CH2, and remap TM3_CH2. |
| 65 | PC8 | bidirectional | 5 V tolerant I/O with default function PC8, alternate TM8_CH3 and remap TM3_CH3. |
| 66 | PC9 | bidirectional | 5 V tolerant I/O with default function PC9, alternate TM8_CH4 and remap TM3_CH4. |
| 67 | PA8 | bidirectional | 5 V tolerant I/O with default function PA8 and alternates USART1_CK, TM1_CH1 and MCO. |
| 68 | PA9 | bidirectional | 5 V tolerant I/O with default function PA9 and alternates USART1_TX, TM1_CH2 and OTG_FS_VBUS. |
| 69 | PA10 | bidirectional | 5 V tolerant I/O with default function PA10 and alternates USART1_RX, TM1_CH3 and OTG_FS_ID. |
| 70 | PA11 | bidirectional | 5 V tolerant I/O with default function PA11 and alternates USART1_CTS, CANRX, OTG_FS_DM and TM1_CH4. |
| 71 | PA12 | bidirectional | 5 V tolerant I/O with default function PA12 and alternates USART1_RTS, OTG_FS_DP, CAN1_TX and TM1_ETR. |
| 72 | PA13 | bidirectional | 5 V tolerant I/O with default function JTMS/SWDIO and remap PA13. |
| 73 | NC | unconnected | Not connected; listed as NC in the LQFP100 column of the pin table. |
| 74 | VSS_2 | power_in | Ground pin VSS_2. |
| 75 | VDD_2 | power_in | Power supply pin VDD_2. |
| 76 | PA14 | bidirectional | 5 V tolerant I/O with default function JTCK/SWCLK and remap PA14. |
| 77 | PA15 | bidirectional | 5 V tolerant I/O with default function JTDI and alternates SPI3_NSS and I2S3_WS; remaps TM2_CH1_ETR, PA15 and SPI1_NSS. |
| 78 | PC10 | bidirectional | 5 V tolerant I/O with default function PC10, alternate UART4_TX, and remaps USART3_TX, SPI3_SCK and I2S3_CK. |
| 79 | PC11 | bidirectional | 5 V tolerant I/O with default function PC11, alternate UART4_RX, and remaps USART3_RX and SPI3_MISO. |
| 80 | PC12 | bidirectional | 5 V tolerant I/O with default function PC12, alternate UART5_TX, and remaps USART3_CK, SPI3_MOSI and I2S3_SD. |
| 81 | PD0 | bidirectional | 5 V tolerant I/O with default function PD0, alternate EXMC_D2, and remaps CAN1_RX and OSC_IN. |
| 82 | PD1 | bidirectional | 5 V tolerant I/O with default function PD1, alternate EXMC_D3, and remaps CAN1_TX and OSC_OUT. |
| 83 | PD2 | bidirectional | 5 V tolerant I/O with default function PD2 and alternates TM3_ETR and UART5_RX. |
| 84 | PD3 | bidirectional | 5 V tolerant I/O with default function PD3, alternate EXMC_CLK and remap USART2_CTS. |
| 85 | PD4 | bidirectional | 5 V tolerant I/O with default function PD4, alternate EXMC_NOE and remap USART2_RTS. |
| 86 | PD5 | bidirectional | 5 V tolerant I/O with default function PD5, alternate EXMC_NWE and remap USART2_TX. |
| 87 | PD6 | bidirectional | 5 V tolerant I/O with default function PD6, alternate EXMC_NWAIT and remap USART2_RX. |
| 88 | PD7 | bidirectional | 5 V tolerant I/O with default function PD7, alternate EXMC_NE1/EXMC_NCE2 and remap USART2_CK. |
| 89 | PB3 | bidirectional | 5 V tolerant I/O with default function JTDO and alternates SPI3_SCK and I2S3_CK; remaps PB3, TRACESWO, TM2_CH2 and SPI1_SCK. |
| 90 | PB4 | bidirectional | 5 V tolerant I/O with default function NJTRST and alternate SPI3_MISO; remaps TM3_CH1, PB4 and SPI1_MISO. |
| 91 | PB5 | bidirectional | I/O with default function PB5 and alternates I2C1_SMBAI, SPI3_MOSI, I2S3_SD, ETH_MII_PPS and ETH_RMII_PPS_OUT; remaps TM3_CH2, SPI1_MOSI and CAN2_RX. |
| 92 | PB6 | bidirectional | 5 V tolerant I/O with default function PB6 and alternates I2C1_SCL and TM4_CH1; remaps USART1_TX and CAN2_TX. |
| 93 | PB7 | bidirectional | 5 V tolerant I/O with default function PB7 and alternates I2C1_SDA, TM4_CH2 and EXMC_NADV; remap USART1_RX. |
| 94 | BOOT0 | input | Input pin BOOT0; boot mode selection is described in section 3.4, which is not in this excerpt. |
| 95 | PB8 | bidirectional | 5 V tolerant I/O with default function PB8 and alternates TM4_CH3 and ETH_MII_TXD3; remaps I2C1_SCL and CAN1_RX; the TM10_CH1 function is footnoted for GD32F107xF/xG only. |
| 96 | PB9 | bidirectional | 5 V tolerant I/O with default function PB9 and alternate TM4_CH4; remaps I2C1_SDA and CAN1_TX; the TM11_CH1 function is footnoted for GD32F107xF/xG only. |
| 97 | PE0 | bidirectional | 5 V tolerant I/O with default function PE0 and alternates TM4_ETR and EXMC_NBL0. |
| 98 | PE1 | bidirectional | 5 V tolerant I/O with default function PE1 and alternate EXMC_NBL1. |
| 99 | VSS_3 | power_in | Ground pin VSS_3. |
| 100 | VDD_3 | power_in | Power supply pin VDD_3. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-100(14x14) |
| Category | Embedded Processors & Controllers |
| Pins | 100 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input voltage on other I/O | VIN |  |  | 4 | V |  | 32 |
| Maximum current for GPIO pins | IIO |  |  | 25 | mA |  | 32 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 32 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 32 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 32 |
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V |  | 32 |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 32 |
| Battery supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 32 |
| Supply current (Deep-Sleep mode) | IDD |  | 0.65 | 1.4 | mA | VDD=VBAT=3.3V, All clock off, LSI on, RTC on, All GPIOs analog mode | 33 |
| Power on reset threshold | VPOR | 2.32 | 2.4 | 2.48 | V |  | 34 |
| Power down reset threshold | VPDR | 2.27 | 2.35 | 2.43 | V |  | 34 |
| Electrostatic discharge voltage (human body model) | VESD(HBM) |  |  | 3000 | V | TA=25 °C; JESD22-A114 | 35 |
| Electrostatic discharge voltage (charge device model) | VESD(CDM) |  |  | 500 | V | TA=25 °C; JESD22-C101 | 35 |
| Static latch-up I-test | LU | -100 |  | 100 | mA | TA=25 °C; JESD78 | 35 |
| Vsupply over voltage |  |  |  | 5.4 | V |  | 35 |
| High speed external oscillator (HSE) frequency | fHSE | 3 | 8 | 32 | MHz | VDD=3.3V | 35 |
| Recommended load capacitance on OSC_IN and OSC_OUT | CHSE |  | 20 | 30 | pF |  | 35 |
| HSE oscillator duty cycle | DHSE | 48 | 50 | 52 | % |  | 35 |
| Low speed external oscillator (LSE) frequency | fLSE |  | 32.768 | 1000 | KHz | VDD=VBAT=3.3V | 36 |
| Recommended load capacitance on OSC32_IN and OSC32_OUT | CLSE |  |  | 15 | pF |  | 36 |
| HSI oscillator frequency accuracy, factory-trimmed | ACCHSI | -2.5 |  | 1.5 | % | VDD=3.3V, TA=-40°C ~+105°C | 36 |
| HSI oscillator frequency accuracy, factory-trimmed | ACCHSI | -1.2 |  | 1.2 | % | VDD=3.3V, TA=0°C ~ +85°C | 36 |
| HSI oscillator frequency accuracy, factory-trimmed | ACCHSI | -1 |  | 1 | % | VDD=3.3V, TA=25°C | 36 |
| Low speed internal oscillator (LSI) frequency | fLSI | 30 | 40 | 60 | KHz | VDD=VBAT=3.3V, TA=-40°C ~ +85°C | 36 |
| PLL input clock frequency | fPLLIN | 1 | 8 | 25 | MHz |  | 37 |
| PLL output clock frequency | fPLL | 16 |  | 108 | MHz |  | 37 |
| Number of guaranteed program/erase cycles before failure (Endurance) | PECYC | 100 |  |  | kcycles | TA=-40°C ~ +85°C | 37 |
| Data retention time | tRET | 20 |  |  | years | TA=125°C | 37 |
| Word programming time | tPROG | 200 |  | 400 | us | TA=-40°C ~ +85°C | 37 |
| Page erase time | tERASE | 60 | 100 | 450 | ms | TA=-40°C ~ +85°C | 37 |
| Standard IO Low level input voltage | VIL | -0.3 |  | 0.95 | V | VDD=2.6V | 37 |
| 5V-tolerant IO Low level input voltage | VIL | -0.3 |  | 0.9 | V | VDD=2.6V | 37 |
| Standard IO High level input voltage | VIH | 1.2 |  | 4 | V | VDD=2.6V | 37 |
| 5V-tolerant IO High level input voltage | VIH | 1.5 |  | 5.5 | V | VDD=2.6V | 37 |
| Low level output voltage | VOL |  |  | 0.2 | V | VDD=2.6V | 37 |
| High level output voltage | VOH | 2.3 |  |  | V | VDD=2.6V | 37 |
| Internal pull-up resistor | RPU | 30 | 40 | 50 | kΩ | VIN=VSS | 37 |
| Internal pull-down resistor | RPD | 30 | 40 | 50 | kΩ | VIN=VDD | 37 |
| ADC operating voltage | VDDA | 2.6 | 3.3 | 3.6 | V |  | 38 |
| ADC input voltage range | VADCIN | 0 |  |  | V |  | 38 |
| ADC clock | fADC | 0.6 |  | 14 | MHz |  | 38 |
| Sampling rate | fS |  |  | 1 | MHz |  | 38 |
| ADC conversion time | fADCCONV | 1 |  | 18 | us | fADC=14MHz | 38 |
| Input sampling switch resistance | RADC |  |  | 0.5 | kΩ |  | 38 |
| DAC operating voltage | VDDA | 2.6 | 3.3 | 3.6 | V |  | 38 |
| DAC input voltage range | VDACIN | 0 |  |  | V |  | 38 |
| Load resistance | RLOAD | 5 |  |  | kΩ | Resistive load vs. VSSA with buffer ON | 38 |
| Load capacitance | CLOAD |  |  | 50 | pF | No pin/pad capacitance included | 38 |
| Differential non-linearity error | DNE | -3 |  | 3 | LSB | DAC in 12-bit | 38 |
| Integral non-linearity | INL | -4 |  | 4 | LSB | DAC in 12-bit | 38 |
| SCL clock frequency | fSCL | 0 |  | 100 | KHz | Standard mode | 38 |
| SCL clock frequency | fSCL | 0 |  | 400 | KHz | Fast mode | 38 |
| SCK clock frequency | fSCK |  |  | 18 | MHz |  | 39 |
| SCK clock high time | tSCK(H) | 19 |  |  | ns |  | 39 |
| SCK clock low time | tSCK(L) | 19 |  |  | ns |  | 39 |
| Data output valid time | tV(MO) |  |  | 25 | ns | SPI master mode | 39 |
| Data output hold time | tH(MO) | 2 |  |  | ns | SPI master mode | 39 |
| Data input setup time | tSU(MI) | 5 |  |  | ns | SPI master mode | 39 |
| Data input hold time | tH(MI) | 5 |  |  | ns | SPI master mode | 39 |

## CAD (KiCad official)

- Symbol: `GD32F107VCT6`
- Footprint: `Package_QFP:LQFP-100_14x14mm_P0.5mm`
- 3D model: LQFP-100(14x14) (KiCad packages3D, STEP)
- 3D model files: `gd32f107vct6-etched.step` / `gd32f107vct6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32f107vct6.step` / `gd32f107vct6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8586175549375467520) (43 pp, sha256 `0b9c0b5aabe0bf30`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32f107vct6-datasheet.pdf)