# GD32F107RCT6

**GigaDevice Semicon Beijing** · Microcontrollers (MCU/MPU/SOC) · LQFP-64(10x10)

GD32F107RCT6 from GigaDevice Semicon Beijing, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup-domain supply pin (Table 2 pin type P, default function VBAT); the extract gives no voltage limit for it. |
| 2 | PC13-TAMPER-RTC | bidirectional | General-purpose I/O PC13 with alternate function TAMPER-RTC; Table 2 gives no 5 V tolerance marking for this pin. |
| 3 | PC14-OSC32_IN | bidirectional | General-purpose I/O PC14 with alternate function OSC32_IN; Table 2 gives no 5 V tolerance marking for this pin. |
| 4 | PC15-OSC32_OUT | bidirectional | General-purpose I/O PC15 with alternate function OSC32_OUT; Table 2 gives no 5 V tolerance marking for this pin. |
| 5 | OSC_IN | input | High-speed external oscillator input (default OSC_IN), which can be remapped to PD0 according to Table 2. |
| 6 | OSC_OUT | output | High-speed external oscillator output (default OSC_OUT), which can be remapped to PD1 according to Table 2. |
| 7 | NRST | bidirectional | Reset pin (default NRST, listed as I/O in Table 2) with no alternate function listed. |
| 8 | PC0 | bidirectional | General-purpose I/O PC0 with alternate function ADC_IN10. |
| 9 | PC1 | bidirectional | General-purpose I/O PC1 with alternate functions ADC_IN11, ETH_MII_MDC and ETH_RMII_MDC. |
| 10 | PC2 | bidirectional | General-purpose I/O PC2 with alternate functions ADC_IN12 and ETH_MII_TXD2. |
| 11 | PC3 | bidirectional | General-purpose I/O PC3 with alternate functions ADC_IN13 and ETH_MII_TX_CLK. |
| 12 | VSSA | power_in | Analog ground pin (default VSSA, Table 2 pin type P). |
| 13 | VDDA | power_in | Analog supply pin (default VDDA, Table 2 pin type P). |
| 14 | PA0-WKUP | bidirectional | General-purpose I/O PA0 with WKUP wake-up function and alternate functions USART2_CTS, ADC_IN0, TM2_CH1_ETR, TM5_CH1, TM8_ETR and ETH_MII_CRS_WKUP. |
| 15 | PA1 | bidirectional | General-purpose I/O PA1 with alternate functions USART2_RTS, ADC_IN1, TM2_CH2, TM5_CH2, ETH_MII_RX_CLK and ETH_RMII_REF_CLK. |
| 16 | PA2 | bidirectional | General-purpose I/O PA2 with alternate functions USART2_TX, ADC_IN2, TM2_CH3, TM5_CH3, ETH_MII_MDIO and ETH_RMII_MDIO. |
| 17 | PA3 | bidirectional | General-purpose I/O PA3 with alternate functions USART2_RX, ADC_IN3, TM2_CH4, TM5_CH4 and ETH_MII_COL. |
| 18 | VSS_4 | power_in | Digital ground pin (default VSS_4, Table 2 pin type P). |
| 19 | VDD_4 | power_in | Digital supply pin (default VDD_4, Table 2 pin type P). |
| 20 | PA4 | bidirectional | General-purpose I/O PA4 with alternate functions SPI1_NSS, USART2_CK, ADC12_IN4 and DAC_OUT1, and remap to SPI3_NSS and I2S3_WS. |
| 21 | PA5 | bidirectional | General-purpose I/O PA5 with alternate functions SPI1_SCK, ADC12_IN5 and DAC_OUT2. |
| 22 | PA6 | bidirectional | General-purpose I/O PA6 with alternate functions SPI1_MISO, ADC12_IN6, TM3_CH1 and TM8_BKIN, and remap to TM1_BKIN. |
| 23 | PA7 | bidirectional | General-purpose I/O PA7 with alternate functions SPI1_MOSI, ADC12_IN7, TM3_CH2, TM8_CH1N, ETH_MII_RX_DV and ETH_RMII_CRS_DV, and remap to TM1_CH1N. |
| 24 | PC4 | bidirectional | General-purpose I/O PC4 with alternate functions ADC12_IN14, ETH_MII_RXD0 and ETH_RMII_RXD0. |
| 25 | PC5 | bidirectional | General-purpose I/O PC5 with alternate functions ADC12_IN15, ETH_MII_RXD1 and ETH_RMII_RXD1. |
| 26 | PB0 | bidirectional | General-purpose I/O PB0 with alternate functions ADC12_IN8, TM3_CH3, TM8_CH2N and ETH_MII_RXD2, and remap to TM1_CH2N. |
| 27 | PB1 | bidirectional | General-purpose I/O PB1 with alternate functions ADC12_IN9, TM3_CH4, TM8_CH3N and ETH_MII_RXD3, and remap to TM1_CH3N. |
| 28 | PB2 | bidirectional | 5 V-tolerant I/O PB2 whose default function is shared with BOOT1. |
| 29 | PB10 | bidirectional | 5 V-tolerant I/O PB10 with alternate functions I2C2_SCL, USART3_TX and ETH_MII_RX_ER, and remap to TM2_CH3. |
| 30 | PB11 | bidirectional | 5 V-tolerant I/O PB11 with alternate functions I2C2_SDA, USART3_RX, ETH_MII_TX_EN and ETH_RMII_TX_EN, and remap to TM2_CH4. |
| 31 | VSS_1 | power_in | Digital ground pin (default VSS_1, Table 2 pin type P). |
| 32 | VDD_1 | power_in | Digital supply pin (default VDD_1, Table 2 pin type P). |
| 33 | PB12 | bidirectional | 5 V-tolerant I/O PB12 with alternate functions SPI2_NSS, I2C2_SMBAI, USART3_CK, TM1_BKIN, I2S2_WS, CAN2_RX, ETH_MII_TXD0 and ETH_RMII_TXD0. |
| 34 | PB13 | bidirectional | 5 V-tolerant I/O PB13 with alternate functions SPI2_SCK, USART3_CTS, TM1_CH1N, I2S2_CK, CAN2_TX, ETH_MII_TXD1 and ETH_RMII_TXD1. |
| 35 | PB14 | bidirectional | 5 V-tolerant I/O PB14 with alternate functions SPI2_MISO, USART3_RTS and TM1_CH2N. |
| 36 | PB15 | bidirectional | 5 V-tolerant I/O PB15 with alternate functions SPI2_MOSI, TM1_CH3N and I2S2_SD. |
| 37 | PC6 | bidirectional | 5 V-tolerant I/O PC6 with alternate functions I2S2_MCK and TM8_CH1, and remap to TM3_CH1. |
| 38 | PC7 | bidirectional | 5 V-tolerant I/O PC7 with alternate functions I2S3_MCK and TM8_CH2, and remap to TM3_CH2. |
| 39 | PC8 | bidirectional | 5 V-tolerant I/O PC8 with alternate function TM8_CH3, and remap to TM3_CH3. |
| 40 | PC9 | bidirectional | 5 V-tolerant I/O PC9 with alternate function TM8_CH4, and remap to TM3_CH4. |
| 41 | PA8 | bidirectional | 5 V-tolerant I/O PA8 with alternate functions USART1_CK, TM1_CH1 and MCO. |
| 42 | PA9 | bidirectional | 5 V-tolerant I/O PA9 with alternate functions USART1_TX, TM1_CH2 and OTG_FS_VBUS. |
| 43 | PA10 | bidirectional | 5 V-tolerant I/O PA10 with alternate functions USART1_RX, TM1_CH3 and OTG_FS_ID. |
| 44 | PA11 | bidirectional | 5 V-tolerant I/O PA11 with alternate functions USART1_CTS, CANRX, OTG_FS_DM and TM1_CH4. |
| 45 | PA12 | bidirectional | 5 V-tolerant I/O PA12 with alternate functions USART1_RTS, OTG_FS_DP, CAN1_TX and TM1_ETR. |
| 46 | PA13 | bidirectional | 5 V-tolerant I/O PA13 whose default function is JTMS/SWDIO, with remap to PA13. |
| 47 | VSS_2 | power_in | Digital ground pin (default VSS_2, Table 2 pin type P). |
| 48 | VDD_2 | power_in | Digital supply pin (default VDD_2, Table 2 pin type P). |
| 49 | PA14 | bidirectional | 5 V-tolerant I/O PA14 whose default function is JTCK/SWCLK, with remap to PA14. |
| 50 | PA15 | bidirectional | 5 V-tolerant I/O PA15 whose default function is JTDI, with alternate functions SPI3_NSS and I2S3_WS and remap to TM2_CH1_ETR, PA15 and SPI1_NSS. |
| 51 | PC10 | bidirectional | 5 V-tolerant I/O PC10 with alternate function UART4_TX, and remap to USART3_TX, SPI3_SCK and I2S3_CK. |
| 52 | PC11 | bidirectional | 5 V-tolerant I/O PC11 with alternate function UART4_RX, and remap to USART3_RX and SPI3_MISO. |
| 53 | PC12 | bidirectional | 5 V-tolerant I/O PC12 with alternate function UART5_TX, and remap to USART3_CK, SPI3_MOSI and I2S3_SD. |
| 54 | PD2 | bidirectional | 5 V-tolerant I/O PD2 with alternate functions TM3_ETR and UART5_RX. |
| 55 | PB3 | bidirectional | 5 V-tolerant I/O PB3 whose default function is JTDO, with alternate functions SPI3_SCK and I2S3_CK, and remap to PB3, TRACESWO, TM2_CH2 and SPI1_SCK. |
| 56 | PB4 | bidirectional | 5 V-tolerant I/O PB4 whose default function is NJTRST, with alternate function SPI3_MISO, and remap to TM3_CH1, PB4 and SPI1_MISO. |
| 57 | PB5 | bidirectional | I/O PB5 with alternate functions I2C1_SMBAI, SPI3_MOSI, I2S3_SD, ETH_MII_PPS and ETH_RMII_PPS_OUT, and remap to TM3_CH2, SPI1_MOSI and CAN2_RX; Table 2 gives no 5 V tolerance marking. |
| 58 | PB6 | bidirectional | 5 V-tolerant I/O PB6 with alternate functions I2C1_SCL and TM4_CH1, and remap to USART1_TX and CAN2_TX. |
| 59 | PB7 | bidirectional | 5 V-tolerant I/O PB7 with alternate functions I2C1_SDA, TM4_CH2 and EXMC_NADV, and remap to USART1_RX. |
| 60 | BOOT0 | input | Boot mode selection input (default BOOT0, Table 2 type I); the extract gives no level limit for it. |
| 61 | PB8 | bidirectional | 5 V-tolerant I/O PB8 with alternate functions TM4_CH3 and ETH_MII_TXD3, and remap to I2C1_SCL and CAN1_RX. |
| 62 | PB9 | bidirectional | 5 V-tolerant I/O PB9 with alternate function TM4_CH4, and remap to I2C1_SDA and CAN1_TX. |
| 63 | VSS_3 | power_in | Digital ground pin (default VSS_3, Table 2 pin type P). |
| 64 | VDD_3 | power_in | Digital supply pin (default VDD_3, Table 2 pin type P). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-64(10x10) |
| Category | Embedded Processors & Controllers |
| Pins | 64 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VDD External voltage range | VDD | -0.3 |  | 3.6 | V |  | 31 |
| VDDA External analog supply voltage | VDDA | -0.3 |  | 3.6 | V |  | 31 |
| VBAT External battery supply voltage | VBAT | -0.3 |  | 3.6 | V |  | 31 |
| Input voltage on 5V tolerant pin | VIN | -0.3 |  |  | V |  | 31 |
| Input voltage on other I/O | VIN | -0.3 |  | 4 | V |  | 31 |
| Maximum current for GPIO pins | IIO |  |  | 25 | mA |  | 31 |
| Operating temperature range | TA | -40 |  | 85 | °C |  | 31 |
| Storage temperature range | TSTG | -55 |  | 150 | °C |  | 31 |
| Maximum junction temperature | TJ |  |  | 125 | °C |  | 31 |
| Supply voltage | VDD | 2.6 | 3.3 | 3.6 | V |  | 31 |
| Analog supply voltage | VDDA | 2.6 | 3.3 | 3.6 | V | Same as VDD | 31 |
| Battery supply voltage | VBAT | 1.8 |  | 3.6 | V |  | 31 |
| Supply current (Deep-Sleep mode) | IDD |  | 0.65 | 1.4 | mA | VDD=VBAT=3.3V, All clock off, LSI on, RTC on, All GPIOs analog mode | 32 |
| Power on reset threshold | VPOR | 2.32 | 2.4 | 2.48 | V |  | 33 |
| Power down reset threshold | VPDR | 2.27 | 2.35 | 2.43 | V |  | 33 |
| HSE oscillator frequency | fHSE | 3 | 8 | 32 | MHz | VDD=3.3V | 34 |
| Recommended load capacitance on OSC_IN and OSC_OUT | CHSE |  | 20 | 30 | pF |  | 34 |
| HSE oscillator duty cycle | DHSE | 48 | 50 | 52 | % |  | 34 |
| LSE oscillator frequency | fLSE |  | 32.768 | 1000 | KHz | VDD=VBAT=3.3V | 35 |
| Recommended load capacitance on OSC32_IN and OSC32_OUT | CLSE |  |  | 15 | pF |  | 35 |
| LSE oscillator duty cycle | DLSE | 48 | 50 | 52 | % |  | 35 |
| HSI oscillator frequency accuracy, factory-trimmed | ACCHSI | -2.5 |  | 1.5 | % | VDD=3.3V, TA=-40°C ~+105°C | 35 |
| HSI oscillator frequency accuracy, factory-trimmed | ACCHSI | -1.2 |  | 1.2 | % | VDD=3.3V, TA=0°C ~ +85°C | 35 |
| HSI oscillator frequency accuracy, factory-trimmed | ACCHSI | -1 |  | 1 | % | VDD=3.3V, TA=25°C | 35 |
| HSI oscillator duty cycle | DHSI | 48 | 50 | 52 | % | VDD=3.3V, fHSI=8MHz | 35 |
| HSI oscillator operating current | IDDHSI |  | 80 | 100 | μA | VDD=3.3V, fHSI=8MHz | 35 |
| Low speed internal oscillator (LSI) frequency | fLSI | 30 | 40 | 60 | KHz | VDD=VBAT=3.3V, TA=-40°C ~ +85°C | 35 |
| LSI oscillator operating current | IDDLSI |  | 1 | 2 | μA | VDD=VBAT=3.3V, TA=25°C | 35 |
| PLL input clock frequency | fPLLIN | 1 | 8 | 25 | MHz |  | 36 |
| PLL output clock frequency | fPLL | 16 |  | 108 | MHz |  | 36 |
| Word programming time | tPROG | 200 |  | 400 | us | TA=-40°C ~ +85°C | 36 |
| Page erase time | tERASE | 60 | 100 | 450 | ms | TA=-40°C ~ +85°C | 36 |
| Standard IO Low level input voltage | VIL | -0.3 |  | 0.95 | V | VDD=2.6V | 36 |
| 5V-tolerant IO Low level input voltage | VIL | -0.3 |  | 0.9 | V | VDD=2.6V | 36 |
| Standard IO High level input voltage | VIH | 1.2 |  | 4 | V | VDD=2.6V | 36 |
| 5V-tolerant IO High level input voltage | VIH | 1.5 |  | 5.5 | V | VDD=2.6V | 36 |
| Low level output voltage | VOL |  |  | 0.2 | V | VDD=2.6V | 36 |
| High level output voltage | VOH | 2.3 |  |  | V | VDD=2.6V | 36 |
| Internal pull-up resistor | RPU | 30 | 40 | 50 | kΩ | VIN=VSS | 36 |
| Internal pull-down resistor | RPD | 30 | 40 | 50 | kΩ | VIN=VDD | 36 |
| ADC input voltage range | VADCIN | 0 |  |  | V |  | 37 |
| ADC clock | fADC | 0.6 |  | 14 | MHz |  | 37 |
| Sampling rate | fS |  |  | 1 | MHz |  | 37 |
| ADC conversion time | fADCCONV | 1 |  | 18 | μs | fADC=14MHz | 37 |
| Input sampling switch resistance | RADC |  |  | 0.5 | kΩ |  | 37 |
| Load resistance | RLOAD | 5 |  |  | kΩ | Resistive load vs. VSSA with buffer ON | 37 |
| Load capacitance | CLOAD |  |  | 50 | pF |  | 37 |
| Differential non-linearity error | DNE | -3 |  | 3 | LSB | DAC in 12-bit | 37 |
| Integral non-linearity | INL | -4 |  | 4 | LSB | DAC in 12-bit | 37 |
| Offset error | Offset | -12 |  | 12 | LSB | DAC in 12-bit, VREF+ = 3.6 V | 37 |
| Gain error | GE | -0.5 |  | 0.5 | % | DAC in 12-bit | 37 |
| SCL clock frequency | fSCL | 0 |  | 100 | KHz | Standard mode | 37 |
| SCL clock frequency | fSCL | 0 |  | 400 | KHz | Fast mode | 37 |
| SCK clock frequency | fSCK |  |  | 18 | MHz |  | 38 |
| SCK clock high time | tSCK(H) | 19 |  |  | ns |  | 38 |
| SCK clock low time | tSCK(L) | 19 |  |  | ns |  | 38 |
| Data output valid time | tV(MO) |  |  | 25 | ns | SPI master mode | 38 |
| Data output hold time | tH(MO) | 2 |  |  | ns | SPI master mode | 38 |
| Data input setup time | tSU(MI) | 5 |  |  | ns | SPI master mode | 38 |
| Data input hold time | tH(MI) | 5 |  |  | ns | SPI master mode | 38 |

## CAD (KiCad official)

- Symbol: `GD32F107RCT6`
- Footprint: `Package_QFP:LQFP-64_10x10mm_P0.5mm`
- 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files: `gd32f107rct6-etched.step` / `gd32f107rct6-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd32f107rct6.step` / `gd32f107rct6.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588883966979530752) (43 pp, sha256 `8869cc2b8d4552f0`, retrieved 2026-10-17, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/gd32f107rct6-datasheet.pdf)