component

GD32E230K6U6

Public Made by Adom

by adom

GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), QFN-32-EP(5x5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentembedded processors & controllersgd32e230k6u6factory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 7d ago
viewers gd32e230k6u6: viewers · Ray 7d ago
gd32e230k6u6-etched.glb Publish 0.1.0 · Ray 7d ago
gd32e230k6u6-etched.step gd32e230k6u6: factory component page (tier=lcsc) · Ray 7d ago
gd32e230k6u6-hero.glb gd32e230k6u6: hero GLB from the etched model (keeps the MPN mark) · Ray 7d ago
gd32e230k6u6-hero.overlay.json Publish 0.1.0 · Ray 7d ago
gd32e230k6u6.glb Publish 0.1.0 · Ray 7d ago
gd32e230k6u6.kicad_mod Publish 0.1.0 · Ray 7d ago
gd32e230k6u6.kicad_sym Publish 0.1.0 · Ray 7d ago
gd32e230k6u6.lbr Publish 0.1.0 · Ray 7d ago
gd32e230k6u6.step Publish 0.1.0 · Ray 7d ago
package.json Publish 0.1.0 · Ray 7d ago
page.json Set visibility: public · Ray 7d ago
README.md Publish 0.1.0 · Ray 7d ago

GD32E230K6U6

GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(5x5)

GD32E230K6U6 from GigaDevice Semicon Beijing, in a QFN-32-EP(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 VDD power_in Main digital supply pin (default function VDD); the datasheet gives no further limits for this pin in the provided text.
2 PF0-OSCIN bidirectional 5 V tolerant GPIO PF0 with alternate function I2C0_SDA and additional function OSCIN (external high-speed oscillator input).
3 PF1-OSCOUT bidirectional 5 V tolerant GPIO PF1 with alternate function I2C0_SCL and additional function OSCOUT (external high-speed oscillator output).
4 NRST bidirectional Reset pin (default function NRST); the datasheet lists it as I/O, with electrical limits given in the NRST pin characteristics section, which is not in the provided text.
5 VDDA power_in Analog supply pin (default function VDDA) for the ADC and other analog circuits; no further limits are given in the provided text.
6 PA0-WKUP bidirectional GPIO PA0 with alternates USART0_CTS, USART1_CTS, CMP_OUT and I2C1_SCL, additional ADC_IN0, CMP_IM6, RTC_TAMP1 and WKUP0 wakeup function.
7 PA1 bidirectional GPIO PA1 with alternates USART0_RTS, USART1_RTS, I2C1_SDA, EVENTOUT and TIMER14_CH0_ON (device-dependent), additional ADC_IN1 and CMP_IP.
8 PA2 bidirectional GPIO PA2 with alternates USART0_TX, USART1_TX and TIMER14_CH0 (device-dependent), additional ADC_IN2 and CMP_IM7.
9 PA3 bidirectional GPIO PA3 with alternates USART0_RX, USART1_RX and TIMER14_CH1 (device-dependent), additional ADC_IN3.
10 PA4 bidirectional GPIO PA4 with alternates SPI0_NSS/I2S0_WS, USART0_CK, USART1_CK, TIMER13_CH0 and SPI1_NSS (device-dependent), additional ADC_IN4 and CMP_IM4.
11 PA5 bidirectional GPIO PA5 with alternates SPI0_SCK and I2S0_CK, additional ADC_IN5 and CMP_IM5.
12 PA6 bidirectional GPIO PA6 with alternates SPI0_MISO/I2S0_MCK, TIMER2_CH0, TIMER0_BRKIN, TIMER15_CH0, EVENTOUT and CMP_OUT, additional ADC_IN6.
13 PA7 bidirectional GPIO PA7 with alternates SPI0_MOSI/I2S0_SD, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0 and EVENTOUT, additional ADC_IN7.
14 PB0 bidirectional GPIO PB0 with alternates TIMER2_CH2, TIMER0_CH1_ON, USART1_RX (device-dependent) and EVENTOUT, additional ADC_IN8.
15 PB1 bidirectional GPIO PB1 with alternates TIMER2_CH3, TIMER13_CH0, TIMER0_CH2_ON and SPI1_SCK (device-dependent), additional ADC_IN9.
16 PB2 bidirectional 5 V tolerant GPIO PB2 with alternate function TIMER2_ETI.
17 VDD power_in Digital supply pin (default function VDD); no further limits are given in the provided text.
18 PA8 bidirectional 5 V tolerant GPIO PA8 with alternates USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX (device-dependent) and EVENTOUT.
19 PA9 bidirectional 5 V tolerant GPIO PA9 with alternates USART0_TX, TIMER0_CH1, I2C0_SCL and CK_OUT; PA9/PA10 pair can be remapped to PA11/PA12 via SYSCFG_CFG0.
20 PA10 bidirectional 5 V tolerant GPIO PA10 with alternates USART0_RX, TIMER0_CH2, TIMER16_BRKIN and I2C0_SDA; PA9/PA10 pair can be remapped to PA11/PA12 via SYSCFG_CFG0.
21 PA11 bidirectional 5 V tolerant GPIO PA11 with alternates USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, SPI1_IO2, I2C0_SMBA and I2C1_SCL (remap of PA9/PA10 pair).
22 PA12 bidirectional 5 V tolerant GPIO PA12 with alternates USART0_RTS, TIMER0_ETI, EVENTOUT, SPI1_IO3, I2C0_TXFRAME and I2C1_SDA (remap of PA9/PA10 pair).
23 PA13 bidirectional 5 V tolerant GPIO PA13 defaulting to SWDIO, with alternates IFRP_OUT and SPI1_MISO.
24 PA14 bidirectional 5 V tolerant GPIO PA14 defaulting to SWCLK, with alternates USART0_TX, USART1_TX (device-dependent) and SPI1_MOSI.
25 PA15 bidirectional 5 V tolerant GPIO PA15 with alternates SPI0_NSS/I2S0_WS, USART0_RX, USART1_RX (device-dependent), SPI1_NSS and EVENTOUT.
26 PB3 bidirectional 5 V tolerant GPIO PB3 with alternates SPI0_SCK/I2S0_CK and EVENTOUT.
27 PB4 bidirectional 5 V tolerant GPIO PB4 with alternates SPI0_MISO/I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME and TIMER16_BRKIN.
28 PB5 bidirectional 5 V tolerant GPIO PB5 with alternates SPI0_MOSI/I2S0_SD, I2C0_SMBA, TIMER15_BRKIN and TIMER2_CH1, additional WKUP5 wakeup function.
29 PB6 bidirectional 5 V tolerant GPIO PB6 with alternates I2C0_SCL, USART0_TX and TIMER15_CH0_ON.
30 PB7 bidirectional 5 V tolerant GPIO PB7 with alternates I2C0_SDA, USART0_RX and TIMER16_CH0_ON.
31 BOOT0 input Boot mode selection input (default function BOOT0).
32 PB8 bidirectional 5 V tolerant GPIO PB8 with alternates I2C0_SCL and TIMER15_CH0.
33 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package QFN-32-EP(5x5)
Category Embedded Processors & Controllers
Pins 33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Input voltage on other I/O VIN 3.6 V 43
Input voltage on 5V tolerant pin, maximum (note 3) VIN 6.5 V 43
Variations between different VDD power pins /ΔVDDx/ 50 mV 43
Variations between different ground pins /VSSX −VSS/ 50 mV 43
Maximum current for GPIO pins IIO -25 25 mA 43
Operating temperature range TA -40 85 °C 43
Storage temperature range TSTG -55 150 °C 43
Maximum junction temperature TJ 125 °C 43
Supply voltage VDD 1.8 3.3 3.6 V 43
Analog supply voltage VDDA 1.8 3.3 3.6 V ADC not used 43
Analog supply voltage VDDA 2.4 3.3 3.6 V ADC used 43
AHB1 clock frequency fHCLK1 0 72 MHz 44
Charge device model ESD voltage VESD(CDM) 2000 V TA = 25 °C; JESD22-C101 52
Human body model ESD voltage VESD(HBM) 6000 V TA = 25 °C; JESD22-A114 52
Static latch-up I-test LU I-test -200 200 mA TA = 25 °C; JESD78 52
Static latch-up supply overvoltage 5.4 V 52
Crystal or ceramic frequency fHXTAL 4 8 32 MHz VDD = 3.3 V 52
Crystal or ceramic duty cycle Ducy(HXTAL) 30 50 70 % 52
External clock source or oscillator frequency (HXTAL bypass) fHXTAL_ext 1 8 50 MHz VDD = 3.3 V 52
Crystal or ceramic duty cycle (LXTAL) Ducy(LXTAL) 30 70 % 53
External clock source or oscillator frequency (LXTAL bypass) fLXTAL_ext 32.768 1000 kHz VDD = 3.3 V 54
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -4 5 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 54
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -2 2 % VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C 54
IRC8M oscillator frequency accuracy, factory-trimmed ACCIRC8M -1 1 % VDD = VDDA = 3.3 V, TA = 25°C 54
IRC8M oscillator duty cycle DIRC8M 45 50 55 % VDD = VDDA = 3.3 V, fIRC8M = 8 MHz 54
Low speed internal oscillator (IRC40K) frequency fIRC40K 30 40 60 kHz VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 54
IRC28M oscillator frequency accuracy, factory-trimmed ACCIRC28M -4 5 % VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C 55
IRC28M oscillator frequency accuracy, factory-trimmed ACCIRC28M -3 3 % VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C 55
IRC28M oscillator frequency accuracy, factory-trimmed ACCIRC28M -2 2 % VDD = VDDA = 3.3 V TA = 25 °C 55
IRC28M oscillator duty cycle DIRC28M 45 50 55 % VDD = VDDA = 3.3 V, fIRC28M = 28 MHz 55
PLL input clock frequency fPLLIN 1 25 MHz 56
PLL output clock frequency fPLLOUT 16 72 MHz 56
PLL lock time tLOCK 300 μs 56
Number of guaranteed program/erase cycles (endurance) PECYC 100 kcycles TA = -40 °C ~ +85 °C 56
Data retention time tRET 10 years 10k cycles at TA = 85 °C 56
Word programming time tPROG 37 42 μs TA = -40 °C ~ + 85 °C 56
Page erase time tERASE 3.2 4 ms TA = -40 °C ~ +85 °C 56
Mass erase time tMERASE 8 10 ms TA = -40 °C ~ +85 °C 56
NRST input low level voltage VIL(NRST) -0.5 0.71 V VDD = VDDA = 1.8 V 56
NRST input high level voltage VIH(NRST) 1.08 V VDD = VDDA = 1.8 V 56
NRST input low level voltage VIL(NRST) -0.5 1.05 V VDD = VDDA = 2.5 V 56
NRST input high level voltage VIH(NRST) 1.42 V VDD = VDDA = 2.5 V 56
NRST input low level voltage VIL(NRST) -0.5 1.4 V VDD = VDDA = 3.3 V 56
NRST input high level voltage VIH(NRST) 1.8 V VDD = VDDA = 3.3 V 57
NRST input low level voltage VIL(NRST) -0.5 1.53 V VDD = VDDA = 3.6 V 57
NRST input high level voltage VIH(NRST) 1.95 V VDD = VDDA = 3.6 V 57
Low level output voltage for an IO pin VOL 0.2 V IIO = +8 mA, VDD = 1.8 V 57
Low level output voltage for an IO pin VOL 0.1 V IIO = +8 mA, VDD = 3.3 V 57
High level output voltage for an IO pin VOH 1.5 V IIO = +8 mA, VDD = 1.8 V 58
High level output voltage for an IO pin VOH 2.3 V IIO = +8 mA, VDD = 2.5 V 58
High level output voltage for an IO pin VOH 3.1 V IIO = +8 mA, VDD = 3.3 V 58
High level output voltage for an IO pin VOH 3.4 V IIO = +8 mA, VDD = 3.6 V 58
Low level output voltage for an IO pin VOL 0.5 V IIO = +20 mA, VDD = 2.5 V 57
Low level output voltage for an IO pin VOL 0.4 V IIO = +20 mA, VDD = 3.3 V 57
Low level output voltage for an IO pin VOL 0.4 V IIO = +20 mA, VDD = 3.6 V 58
High level output voltage for an IO pin VOH 1.9 V IIO = +20 mA, VDD = 2.5 V 58
High level output voltage for an IO pin VOH 2.8 V IIO = +20 mA, VDD = 3.3 V 58

CAD (KiCad official)

  • Symbol: GD32E230K6U6
  • Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
  • 3D model: QFN-32-EP(5x5) (KiCad packages3D, STEP)
  • 3D model files: gd32e230k6u6-etched.step / gd32e230k6u6-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd32e230k6u6.step / gd32e230k6u6.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (76 pp, sha256 d410a03c442e14b3, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF