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GD32E230K6T6
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GigaDevice Semicon Beijing Microcontrollers (MCU/MPU/SOC), LQFP-32(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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PCB Footprint
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Datasheet
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README
markdownGD32E230K6T6
GigaDevice Semicon Beijing · Microcontrollers (MCU/MPU/SOC) · LQFP-32(7x7)
GD32E230K6T6 from GigaDevice Semicon Beijing, in a LQFP-32(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Main power supply pin (default function VDD) of the LQFP32 package; the voltage limits are not given in the pin table. |
| 2 | PF0-OSCIN | bidirectional | Port F bit 0 (default PF0), 5 V tolerant, with alternate I2C0_SDA and additional function OSCIN as the high-speed oscillator input. |
| 3 | PF1-OSCOUT | bidirectional | Port F bit 1 (default PF1), 5 V tolerant, with alternate I2C0_SCL and additional function OSCOUT as the high-speed oscillator output. |
| 4 | NRST | bidirectional | Device reset pin (default NRST); its electrical characteristics are given in datasheet section 4.11, not in the pin table. |
| 5 | VDDA | power_in | Analog power supply pin (default function VDDA) for the on-chip analog circuitry such as the ADC. |
| 6 | PA0-WKUP | bidirectional | Port A bit 0 (default PA0) with alternate USART1_CTS, CMP_OUT, additional ADC_IN0, CMP_IM6, RTC_TAMP1 and wakeup function WKUP0. |
| 7 | PA1 | bidirectional | Port A bit 1 (default PA1) with alternate USART1_RTS and EVENTOUT, and additional ADC_IN1 and CMP_IP. |
| 8 | PA2 | bidirectional | Port A bit 2 (default PA2) with alternate USART1_TX, and additional ADC_IN2 and CMP_IM7. |
| 9 | PA3 | bidirectional | Port A bit 3 (default PA3) with alternate USART1_RX, and additional ADC_IN3. |
| 10 | PA4 | bidirectional | Port A bit 4 (default PA4) with alternate SPI0_NSS, I2S0_WS, USART1_CK and TIMER13_CH0, and additional ADC_IN4 and CMP_IM4. |
| 11 | PA5 | bidirectional | Port A bit 5 (default PA5) with alternate SPI0_SCK and I2S0_CK, and additional ADC_IN5 and CMP_IM5. |
| 12 | PA6 | bidirectional | Port A bit 6 (default PA6) with alternate SPI0_MISO, I2S0_MCK, TIMER2_CH0, TIMER0_BRKIN, TIMER15_CH0, EVENTOUT and CMP_OUT, and additional ADC_IN6. |
| 13 | PA7 | bidirectional | Port A bit 7 (default PA7) with alternate SPI0_MOSI, I2S0_SD, TIMER2_CH1, TIMER13_CH0, TIMER0_CH0_ON, TIMER16_CH0 and EVENTOUT, and additional ADC_IN7. |
| 14 | PB0 | bidirectional | Port B bit 0 (default PB0) with alternate TIMER2_CH2, TIMER0_CH1_ON, USART1_RX and EVENTOUT, and additional ADC_IN8. |
| 15 | PB1 | bidirectional | Port B bit 1 (default PB1) with alternate TIMER2_CH3, TIMER13_CH0 and TIMER0_CH2_ON, and additional ADC_IN9. |
| 16 | VSS | power_in | Ground pin (default function VSS) of the LQFP32 package. |
| 17 | VDD | power_in | Main power supply pin (default function VDD) of the LQFP32 package; the voltage limits are not given in the pin table. |
| 18 | PA8 | bidirectional | 5 V tolerant port A bit 8 (default PA8) with alternate USART0_CK, TIMER0_CH0, CK_OUT, USART1_TX and EVENTOUT. |
| 19 | PA9 | bidirectional | 5 V tolerant port A bit 9 (default PA9) with alternate USART0_TX, TIMER0_CH1, I2C0_SCL and CK_OUT. |
| 20 | PA10 | bidirectional | 5 V tolerant port A bit 10 (default PA10) with alternate USART0_RX, TIMER0_CH2, TIMER16_BRKIN and I2C0_SDA. |
| 21 | PA11 | bidirectional | 5 V tolerant port A bit 11 (default PA11) with alternate USART0_CTS, TIMER0_CH3, CMP_OUT, EVENTOUT, I2C0_SMBA. |
| 22 | PA12 | bidirectional | 5 V tolerant port A bit 12 (default PA12) with alternate USART0_RTS, TIMER0_ETI, EVENTOUT and I2C0_TXFRAME. |
| 23 | PA13 | bidirectional | 5 V tolerant port A bit 13 (default PA13/SWDIO) with alternate function SWDIO for the serial-wire debug data line, and IFRP_OUT. |
| 24 | PA14 | bidirectional | 5 V tolerant port A bit 14 (default PA14/SWCLK) with alternate function SWCLK for serial-wire debug clock, and USART1_TX. |
| 25 | PA15 | bidirectional | 5 V tolerant port A bit 15 (default PA15) with alternate SPI0_NSS, I2S0_WS, USART1_RX and EVENTOUT. |
| 26 | PB3 | bidirectional | 5 V tolerant port B bit 3 (default PB3) with alternate SPI0_SCK, I2S0_CK and EVENTOUT. |
| 27 | PB4 | bidirectional | 5 V tolerant port B bit 4 (default PB4) with alternate SPI0_MISO, I2S0_MCK, TIMER2_CH0, EVENTOUT, I2C0_TXFRAME and TIMER16_BRKIN. |
| 28 | PB5 | bidirectional | 5 V tolerant port B bit 5 (default PB5) with alternate SPI0_MOSI, I2S0_SD, I2C0_SMBA, TIMER15_BRKIN and TIMER2_CH1, and additional wakeup function WKUP5. |
| 29 | PB6 | bidirectional | 5 V tolerant port B bit 6 (default PB6) with alternate I2C0_SCL, USART0_TX and TIMER15_CH0_ON. |
| 30 | PB7 | bidirectional | 5 V tolerant port B bit 7 (default PB7) with alternate I2C0_SDA, USART0_RX and TIMER16_CH0_ON. |
| 31 | BOOT0 | input | Boot mode selection input (default function BOOT0); its electrical limits are not stated in the pin table. |
| 32 | VSS | power_in | Ground pin (default function VSS) of the LQFP32 package. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-32(7x7) |
| Category | Embedded Processors & Controllers |
| Pins | 32 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External voltage range (VDD) | VDD | -0.3 | 3.6 | V | Relative to VSS (printed VSS - 0.3 / VSS + 3.6) | 43 | |
| External analog supply voltage (VDDA) | VDDA | -0.3 | 3.6 | V | Relative to VSSA (printed VSSA - 0.3 / VSSA + 3.6) | 43 | |
| Input voltage on 5V tolerant pin | VIN | -0.3 | V | Printed max VDD + 3.6 V; VIN max cannot exceed 6.5 V | 43 | ||
| Input voltage on other I/O | VIN | -0.3 | 3.6 | V | Relative to VSS | 43 | |
| Variations between different VDD power pins | /ΔVDDx/ | 50 | mV | 43 | |||
| Variations between different ground pins | /VSSX −VSS/ | 50 | mV | 43 | |||
| Maximum current for GPIO pins | IIO | -25 | 25 | mA | 43 | ||
| Operating temperature range | TA | -40 | 85 | °C | 43 | ||
| Storage temperature range | TSTG | -55 | 150 | °C | 43 | ||
| Maximum junction temperature | TJ | 125 | °C | 43 | |||
| Supply voltage | VDD | 1.8 | 3.3 | 3.6 | V | 43 | |
| Analog supply voltage (ADC not used) | VDDA | 1.8 | 3.3 | 3.6 | V | ADC not used | 43 |
| Analog supply voltage (ADC used) | VDDA | 2.4 | 3.3 | 3.6 | V | ADC used | 43 |
| AHB1 clock frequency | fHCLK1 | 0 | 72 | MHz | Guaranteed by design, not tested in production | 44 | |
| AHB2 clock frequency | fHCLK2 | 0 | 72 | MHz | Guaranteed by design, not tested in production | 44 | |
| APB1 clock frequency | fAPB1 | 0 | 72 | MHz | Guaranteed by design, not tested in production | 44 | |
| APB2 clock frequency | fAPB2 | 0 | 72 | MHz | Guaranteed by design, not tested in production | 44 | |
| VDD rise time rate | tVDD | 0 | μs /V | Printed max is ∞ | 44 | ||
| VDD fall time rate | tVDD | 20 | μs /V | Printed max is ∞ | 44 | ||
| Electrostatic discharge voltage (human body model) | VESD(HBM) | 6000 | V | TA = 25 °C; JESD22-A114 | 52 | ||
| Electrostatic discharge voltage (charge device model) | VESD(CDM) | 2000 | V | TA = 25 °C; JESD22-C101 | 52 | ||
| Static latch-up I-test | I-test | -200 | 200 | mA | TA = 25 °C; JESD78 | 52 | |
| Latch-up Vsupply over voltage | 5.4 | V | 52 | ||||
| Crystal or ceramic frequency (HXTAL) | fHXTAL | 4 | 8 | 32 | MHz | VDD = 3.3 V | 52 |
| Recommended matching capacitance on OSCIN and OSCOUT | CHXTAL | 20 | 30 | pF | 52 | ||
| Crystal or ceramic duty cycle (HXTAL) | Ducy(HXTAL) | 30 | 50 | 70 | % | 52 | |
| External clock source or oscillator frequency (HXTAL bypass) | fHXTAL_ext | 1 | 8 | 50 | MHz | VDD = 3.3 V | 52 |
| IRC8M oscillator frequency accuracy, factory-trimmed | ACCIRC8M | -4 | 5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 54 | |
| IRC8M oscillator frequency accuracy, factory-trimmed | ACCIRC8M | -2 | 2 | % | VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C | 54 | |
| IRC8M oscillator frequency accuracy, factory-trimmed | ACCIRC8M | -1 | 1 | % | VDD = VDDA = 3.3 V, TA = 25°C | 54 | |
| Low speed internal oscillator frequency (IRC40K) | fIRC40K | 30 | 40 | 60 | kHz | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 54 |
| IRC28M oscillator frequency accuracy, factory-trimmed | ACCIRC28M | -4 | 5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 55 | |
| IRC28M oscillator frequency accuracy, factory-trimmed | ACCIRC28M | -3 | 3 | % | VDD = VDDA = 3.3 V, TA = 0 °C ~ +85 °C | 55 | |
| IRC28M oscillator frequency accuracy, factory-trimmed | ACCIRC28M | -2 | 2 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 55 | |
| PLL input clock frequency | fPLLIN | 1 | 25 | MHz | 56 | ||
| PLL output clock frequency | fPLLOUT | 16 | 72 | MHz | 56 | ||
| PLL VCO output clock frequency | fVCO | 72 | MHz | 56 | |||
| PLL lock time | tLOCK | 300 | μs | 56 | |||
| Number of guaranteed program/erase cycles before failure (Endurance) | PECYC | 100 | kcycles | TA = -40 °C ~ +85 °C | 56 | ||
| Data retention time | tRET | 10 | years | 10k cycles at TA = 85 °C | 56 | ||
| Word programming time | tPROG | 37 | 42 | μs | TA = -40 °C ~ + 85 °C | 56 | |
| Page erase time | tERASE | 3.2 | 4 | ms | TA = -40 °C ~ + 85 °C | 56 | |
| Mass erase time | tMERASE | 8 | 10 | ms | TA = -40 °C ~ + 85°C | 56 | |
| NRST Input low level voltage | VIL(NRST) | -0.5 | 1.4 | V | VDD = VDDA = 3.3 V | 56 | |
| NRST Input high level voltage | VIH(NRST) | 1.8 | V | 57 | |||
| Low level output voltage for an IO Pin (IIO = +8 mA) | VOL | 0.2 | V | IIO = +8 mA; VDD = 1.8 V | 57 | ||
| Low level output voltage for an IO Pin (IIO = +8 mA) | VOL | 0.1 | V | IIO = +8 mA; VDD = 3.3 V | 57 | ||
| Low level output voltage for an IO Pin (IIO = +20 mA) | VOL | 0.5 | V | IIO = +20 mA; VDD = 2.5 V | 57 | ||
| Low level output voltage for an IO Pin (IIO = +20 mA) | VOL | 0.4 | V | IIO = +20 mA; VDD = 3.3 V | 57 | ||
| Low level output voltage for an IO Pin (IIO = +20 mA) | VOL | 0.4 | V | IIO = +20 mA; VDD = 3.6 V | 58 | ||
| High level output voltage for an IO Pin (IIO = +8 mA) | VOH | 1.5 | V | IIO = +8 mA; VDD = 1.8 V | 58 | ||
| High level output voltage for an IO Pin (IIO = +8 mA) | VOH | 2.3 | V | IIO = +8 mA; VDD = 2.5 V | 58 | ||
| High level output voltage for an IO Pin (IIO = +8 mA) | VOH | 3.1 | V | IIO = +8 mA; VDD = 3.3 V | 58 | ||
| High level output voltage for an IO Pin (IIO = +8 mA) | VOH | 3.4 | V | IIO = +8 mA; VDD = 3.6 V | 58 | ||
| High level output voltage for an IO Pin (IIO = +20 mA) | VOH | 1.9 | V | IIO = +20 mA; VDD = 2.5 V | 58 | ||
| High level output voltage for an IO Pin (IIO = +20 mA) | VOH | 2.8 | V | IIO = +20 mA; VDD = 3.3 V | 58 | ||
| High level output voltage for an IO Pin (IIO = +20 mA) | VOH | 3.1 | V | IIO = +20 mA; VDD = 3.6 V | 58 | ||
| ADC clock | fADC | 0.1 | 28 | MHz | 59 |
CAD (KiCad official)
- Symbol:
GD32E230K6T6 - Footprint:
Package_QFP:LQFP-32_7x7mm_P0.8mm - 3D model: LQFP-32(7x7) (KiCad packages3D, STEP)
- 3D model files:
gd32e230k6t6-etched.step/gd32e230k6t6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gd32e230k6t6.step/gd32e230k6t6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice Semicon Beijing datasheet (76 pp, sha256
8475f6cb65c55913, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).