component
GD32E103R8T6
Public Made by Adomby adom
GigaDevice Semicon Beijing Microcontroller Units (MCUs/MPUs/SOCs), LQFP-64(10x10). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
Generated by kicad-footprint-generator · KiCad file format 20260206
| Name | Last updated |
|---|---|
| docs | 5d ago |
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| gd32e103r8t6-etched.glb | 5d ago |
| gd32e103r8t6-etched.step | 5d ago |
| gd32e103r8t6-hero.glb | 5d ago |
| gd32e103r8t6-hero.overlay.json | 5d ago |
| gd32e103r8t6.glb | 5d ago |
| gd32e103r8t6.kicad_mod | 5d ago |
| gd32e103r8t6.kicad_sym | 5d ago |
| gd32e103r8t6.lbr | 5d ago |
| gd32e103r8t6.step | 5d ago |
| package.json | 5d ago |
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| README.md | 5d ago |
GD32E103R8T6
GigaDevice Semicon Beijing · Microcontroller Units (MCUs/MPUs/SOCs) · LQFP-64(10x10)
GD32E103R8T6 from GigaDevice Semicon Beijing, in a LQFP-64(10x10). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VBAT | power_in | Backup battery supply pin for the RTC and backup domain. |
| 2 | PC13-TAMPER-RTC | bidirectional | GPIO PC13 with alternate function RTC_TAMPER. |
| 3 | PC14-OSC32IN | bidirectional | GPIO PC14 with alternate function OSC32IN (32.768 kHz crystal input). |
| 4 | PC15-OSC32OUT | bidirectional | GPIO PC15 with alternate function OSC32OUT (32.768 kHz crystal output). |
| 5 | PD0-OSCIN | input | Default OSCIN (HXTAL oscillator input), remappable to PD0 (cannot be used for EXTI in this package). |
| 6 | PD1-OSCOUT | output | Default OSCOUT (HXTAL oscillator output), remappable to PD1 (cannot be used for EXTI in this package). |
| 7 | NRST | bidirectional | System reset pin, default function NRST. |
| 8 | PC0 | bidirectional | GPIO PC0 with alternate function ADC01_IN10. |
| 9 | PC1 | bidirectional | GPIO PC1 with alternate function ADC01_IN11. |
| 10 | PC2 | bidirectional | GPIO PC2 with alternate function ADC01_IN12. |
| 11 | PC3 | bidirectional | GPIO PC3 with alternate function ADC01_IN13. |
| 12 | VSSA | power_in | Analog ground. |
| 13 | VDDA | power_in | Analog power supply (VREF+ is internally connected to VDDA in this package). |
| 14 | PA0-WKUP | bidirectional | GPIO PA0 with alternate functions WKUP, USART1_CTS, ADC01_IN0, TIMER1_CH0, TIMER1_ETI, TIMER4_CH0, TIMER7_ETI. |
| 15 | PA1 | bidirectional | GPIO PA1 with alternate functions USART1_RTS/USART1_DE, ADC01_IN1, TIMER4_CH1, TIMER1_CH1. |
| 16 | PA2 | bidirectional | GPIO PA2 with alternate functions USART1_TX, TIMER4_CH2, ADC01_IN2, TIMER8_CH0, TIMER1_CH2, SPI0_IO2. |
| 17 | PA3 | bidirectional | GPIO PA3 with alternate functions USART1_RX, TIMER4_CH3, ADC01_IN3, TIMER1_CH3, TIMER8_CH1, SPI0_IO3. |
| 18 | VSS_4 | power_in | Digital ground. |
| 19 | VDD_4 | power_in | Digital power supply. |
| 20 | PA4 | bidirectional | GPIO PA4 with alternate functions SPI0_NSS, USART1_CK, DAC_OUT0, ADC01_IN4; remap SPI2_NSS, I2S2_WS. |
| 21 | PA5 | bidirectional | GPIO PA5 with alternate functions SPI0_SCK, ADC01_IN5, DAC_OUT1. |
| 22 | PA6 | bidirectional | GPIO PA6 with alternate functions SPI0_MISO, TIMER7_BRKIN, ADC01_IN6, TIMER2_CH0, TIMER12_CH0; remap TIMER0_BRKIN. |
| 23 | PA7 | bidirectional | GPIO PA7 with alternate functions SPI0_MOSI, TIMER7_CH0_ON, ADC01_IN7, TIMER2_CH1, TIMER13_CH0; remap TIMER0_CH0_ON. |
| 24 | PC4 | bidirectional | GPIO PC4 with alternate function ADC01_IN14. |
| 25 | PC5 | bidirectional | GPIO PC5 with alternate function ADC01_IN15. |
| 26 | PB0 | bidirectional | GPIO PB0 with alternate functions ADC01_IN8, TIMER2_CH2, TIMER7_CH1_ON; remap TIMER0_CH1_ON. |
| 27 | PB1 | bidirectional | GPIO PB1 with alternate functions ADC01_IN9, TIMER2_CH3, TIMER7_CH2_ON; remap TIMER0_CH2_ON. |
| 28 | PB2 | bidirectional | 5V-tolerant GPIO PB2, also BOOT1. |
| 29 | PB10 | bidirectional | 5V-tolerant GPIO PB10 with alternate functions I2C1_SCL, USART2_TX; remap TIMER1_CH2. |
| 30 | PB11 | bidirectional | 5V-tolerant GPIO PB11 with alternate functions I2C1_SDA, USART2_RX; remap TIMER1_CH3. |
| 31 | VSS_1 | power_in | Digital ground. |
| 32 | VDD_1 | power_in | Digital power supply. |
| 33 | PB12 | bidirectional | 5V-tolerant GPIO PB12 with alternate functions SPI1_NSS, I2S1_WS, I2C1_SMBA, USART2_CK, TIMER0_BRKIN. |
| 34 | PB13 | bidirectional | 5V-tolerant GPIO PB13 with alternate functions SPI1_SCK, I2S1_CK, USART2_CTS, TIMER0_CH0_ON, I2C1_TXFRAME. |
| 35 | PB14 | bidirectional | 5V-tolerant GPIO PB14 with alternate functions SPI1_MISO, USART2_RTS/USART2_DE, TIMER0_CH1_ON, TIMER11_CH0. |
| 36 | PB15 | bidirectional | 5V-tolerant GPIO PB15 with alternate functions SPI1_MOSI, I2S1_SD, TIMER0_CH2_ON, TIMER11_CH1. |
| 37 | PC6 | bidirectional | 5V-tolerant GPIO PC6 with alternate functions I2S1_MCK, TIMER7_CH0; remap TIMER2_CH0. |
| 38 | PC7 | bidirectional | 5V-tolerant GPIO PC7 with alternate functions I2S2_MCK, TIMER7_CH1; remap TIMER2_CH1. |
| 39 | PC8 | bidirectional | 5V-tolerant GPIO PC8 with alternate function TIMER7_CH2; remap TIMER2_CH2. |
| 40 | PC9 | bidirectional | 5V-tolerant GPIO PC9 with alternate function TIMER7_CH3; remap TIMER2_CH3. |
| 41 | PA8 | bidirectional | 5V-tolerant GPIO PA8 with alternate functions USART0_CK, TIMER0_CH0, CK_OUT0, VCORE, USBFS_SOF, CTC_SYNC. |
| 42 | PA9 | bidirectional | 5V-tolerant GPIO PA9 with alternate functions USART0_TX, TIMER0_CH1, USBFS_VBUS. |
| 43 | PA10 | bidirectional | 5V-tolerant GPIO PA10 with alternate functions USART0_RX, TIMER0_CH2, USBFS_ID, V1REF. |
| 44 | PA11 | bidirectional | 5V-tolerant GPIO PA11 with alternate functions USART0_CTS, USBFS_DM, TIMER0_CH3. |
| 45 | PA12 | bidirectional | 5V-tolerant GPIO PA12 with alternate functions USART0_RTS/USART0_DE, USBFS_DP, TIMER0_ETI. |
| 46 | PA13 | bidirectional | 5V-tolerant pin, default JTMS/SWDIO, remappable to PA13. |
| 47 | VSS_2 | power_in | Digital ground. |
| 48 | VDD_2 | power_in | Digital power supply. |
| 49 | PA14 | bidirectional | 5V-tolerant pin, default JTCK/SWCLK, remappable to PA14. |
| 50 | PA15 | bidirectional | 5V-tolerant pin, default JTDI; alternate SPI2_NSS, I2S2_WS; remap TIMER1_CH0, TIMER1_ETI, PA15, SPI0_NSS. |
| 51 | PC10 | bidirectional | 5V-tolerant GPIO PC10 with alternate function UART3_TX; remap USART2_TX, SPI2_SCK, I2S2_CK. |
| 52 | PC11 | bidirectional | 5V-tolerant GPIO PC11 with alternate function UART3_RX; remap USART2_RX, SPI2_MISO. |
| 53 | PC12 | bidirectional | 5V-tolerant GPIO PC12 with alternate function UART4_TX; remap USART2_CK, SPI2_MOSI, I2S2_SD. |
| 54 | PD2 | bidirectional | 5V-tolerant GPIO PD2 with alternate functions TIMER2_ETI, UART4_RX. |
| 55 | PB3 | bidirectional | 5V-tolerant pin, default JTDO; alternate SPI2_SCK, I2S2_CK; remap TIMER1_CH1, PB3, SPI0_SCK. |
| 56 | PB4 | bidirectional | 5V-tolerant pin, default NJTRST; alternate SPI2_MISO, I2C0_TXFRAME; remap TIMER2_CH0, PB4, SPI0_MISO. |
| 57 | PB5 | bidirectional | GPIO PB5 (not 5V tolerant) with alternate functions I2C0_SMBA, SPI2_MOSI, I2S2_SD; remap TIMER2_CH1, SPI0_MOSI. |
| 58 | PB6 | bidirectional | 5V-tolerant GPIO PB6 with alternate functions I2C0_SCL, TIMER3_CH0; remap USART0_TX, SPI0_IO2. |
| 59 | PB7 | bidirectional | 5V-tolerant GPIO PB7 with alternate functions I2C0_SDA, TIMER3_CH1; remap USART0_RX, SPI0_IO3. |
| 60 | BOOT0 | input | Boot mode selection input, default function BOOT0. |
| 61 | PB8 | bidirectional | 5V-tolerant GPIO PB8 with alternate functions TIMER3_CH2, TIMER9_CH0; remap I2C0_SCL. |
| 62 | PB9 | bidirectional | 5V-tolerant GPIO PB9 with alternate functions TIMER3_CH3, TIMER10_CH0; remap I2C0_SDA. |
| 63 | VSS_3 | power_in | Digital ground. |
| 64 | VDD_3 | power_in | Digital power supply. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | LQFP-64(10x10) |
| Category | Single Chip Microcomputer/Microcontroller |
| Pins | 64 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| External voltage range | VDD | 3.6 | V | VSS - 0.3 to VSS + 3.6 (min = VSS - 0.3) | 42 | ||
| External analog supply voltage | VDDA | 3.6 | V | VSSA - 0.3 to VSSA + 3.6 | 42 | ||
| External battery supply voltage | VBAT | 3.6 | V | VSS - 0.3 to VSS + 3.6 | 42 | ||
| Input voltage on other I/O | VIN | 3.6 | V | VSS - 0.3 min | 42 | ||
| Variations between different VDD power pins | /ΔVDDX/ | 50 | mV | 42 | |||
| Variations between different ground pins | /VSSX −VSS/ | 50 | mV | 42 | |||
| Maximum current for GPIO pins | IIO | -25 | 25 | mA | 42 | ||
| Operating temperature range | TA | -40 | 85 | °C | 42 | ||
| Power dissipation LQFP64 | PD | 733 | mW | TA = 85°C of LQFP64 | 42 | ||
| Storage temperature range | TSTG | -65 | 150 | °C | 42 | ||
| Maximum junction temperature | TJ | 125 | °C | 42 | |||
| Supply voltage | VDD | 1.71 | 3.3 | 3.6 | V | 42 | |
| Analog supply voltage, ADC not used | VDDA | 1.71 | 3.3 | 3.6 | V | ADC not used | 42 |
| Analog supply voltage, ADC used | VDDA | 2.4 | 3.3 | 3.6 | V | ADC used | 42 |
| Battery supply voltage | VBAT | 1.71 | 3.6 | V | 42 | ||
| AHB clock frequency | fHCLK | 120 | MHz | 43 | |||
| APB1 clock frequency | fAPB1 | 60 | MHz | 43 | |||
| APB2 clock frequency | fAPB2 | 120 | MHz | 43 | |||
| VDD fall time rate | tVDD | 20 | μs/V | VDD fall time rate | 43 | ||
| VDD rise time rate | tVDD | 0 | μs/V | VDD rise time rate | 43 | ||
| Thermal resistance junction-to-ambient LQFP64 | ΘJA | 54.57 | °C/W | Natural convection, 2S2P PCB, LQFP64 | 83 | ||
| Thermal resistance junction-to-board LQFP64 | ΘJB | 35.08 | °C/W | Cold plate, 2S2P PCB, LQFP64 | 83 | ||
| Thermal resistance junction-to-case LQFP64 | ΘJC | 18.11 | °C/W | Cold plate, 2S2P PCB, LQFP64 | 84 | ||
| Junction-to-board characterization parameter LQFP64 | ΨJB | 35.41 | °C/W | Natural convection, 2S2P PCB, LQFP64 | 84 | ||
| Junction-to-top characterization parameter LQFP64 | ΨJT | 1.1 | °C/W | Natural convection, 2S2P PCB, LQFP64 | 84 | ||
| LVD hysteresis | VLVDhyst | 100 | mV | 52 | |||
| Power on reset threshold | VPOR | 1.67 | V | 52 | |||
| Power down reset threshold | VPDR | 1.62 | V | 52 | |||
| HBM ESD voltage | VESD(HBM) | 5000 | V | TA = 25 °C; JS-001-2014 | 52 | ||
| CDM ESD voltage | VESD(CDM) | 800 | V | TA = 25 °C; JS-002-2014 | 53 | ||
| Latch-up I-test | LU | 200 | mA | TA = 25 °C; JESD78 (±200) | 54 | ||
| Crystal or ceramic frequency | fHXTAL | 4 | 8 | 32 | MHz | 1.71 ≤ VDD ≤ 3.6 V | 54 |
| IRC8M accuracy, factory-trimmed | ACCIRC8M | -2.5 | 2.5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 56 | |
| IRC8M accuracy, factory-trimmed | ACCIRC8M | -1 | 1 | % | VDD = VDDA = 3.3 V, TA = 25 °C | 56 | |
| IRC40K frequency | fIRC40K | 28 | 40 | 60 | kHz | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 56 |
| IRC48M accuracy, factory-trimmed | ACCIRC48M | -4 | 5 | % | VDD = VDDA = 3.3 V, TA = -40 °C ~ +85 °C | 57 | |
| PLL input clock frequency | fPLLIN | 1 | 8 | 25 | MHz | 57 | |
| PLL output clock frequency | fPLLOUT | 16 | 120 | MHz | 57 | ||
| PLL lock time | tLOCK | 300 | μs | 57 | |||
| Flash endurance | PECYC | 100 | kcycles | TA = -40 °C ~ +85 °C | 58 | ||
| Flash data retention | tRET | 10 | years | 10k cycles at TA = 85 °C | 58 | ||
| Word programming time | tPROG | 37 | 44 | μs | TA = -40 °C ~ +85 °C | 58 | |
| Page erase time | tERASE | 3.2 | 4 | ms | TA = -40 °C ~ +85 °C | 58 | |
| NRST input low level voltage | VIL(NRST) | -0.5 | 0.3 | V | 1.8 V ≤ VDD = VDDA ≤ 3.6 V (max = 0.3 VDD) | 58 | |
| NRST input high level voltage | VIH(NRST) | 0.7 | 0.45 | V | 1.8 V ≤ VDD = VDDA ≤ 3.6 V (min = 0.7 VDD, max = VDD + 0.45) | 58 | |
| Standard IO low level input voltage | VIL | 0.3 | V | 1.8 V ≤ VDD = VDDA ≤ 3.6 V (max = 0.3 VDD) | 59 | ||
| Standard IO high level input voltage | VIH | 0.7 | V | 1.8 V ≤ VDD = VDDA ≤ 3.6 V (min = 0.7 VDD) | 59 | ||
| Low level output voltage (IIO = +8 mA) | VOL | 0.32 | V | VDD = 1.8 V | 59 | ||
| Low level output voltage (IIO = +20 mA) | VOL | 0.28 | V | VDD = 3.3 V | 59 | ||
| High level output voltage (IIO = +8 mA) | VOH | 3.14 | V | VDD = 3.3 V | 59 | ||
| High level output voltage (IIO = +20 mA) | VOH | 2.91 | V | VDD = 3.3 V | 59 | ||
| ADC operating voltage | VDDA | 2.4 | 3.3 | 3.6 | V | 61 | |
| ADC clock | fADC | 0.1 | 42 | MHz | 61 | ||
| ADC external input impedance | RAIN | 24 | kΩ | See Equation 1 | 61 | ||
| DAC operating voltage | VDDA | 1.71 | 3.3 | 3.6 | V | 63 | |
| DAC INL | INL | 4 | LSB | DAC in 12-bit mode (±4) | 63 | ||
| Supply current (Run mode) | IDD+IDDA | 28.1 | mA | VDD = VDDA = 3.3 V, HXTAL = 25 MHz, System clock=120 MHz, All peripherals enabled | 44 |
CAD (KiCad official)
- Symbol:
GD32E103R8T6 - Footprint:
Package_QFP:LQFP-64_10x10mm_P0.5mm - 3D model: LQFP-64(10x10) (KiCad packages3D, STEP)
- 3D model files:
gd32e103r8t6-etched.step/gd32e103r8t6-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gd32e103r8t6.step/gd32e103r8t6.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice Semicon Beijing datasheet (88 pp, sha256
dc81c0f7bc7a3a61, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).