component
GD25Q80CSIG
Public Made by Adomby adom
GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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GD25Q80CSIG
GigaDevice Semicon Beijing · NOR FLASH · SOP-8-208mil
GD25Q80CSIG from GigaDevice Semicon Beijing, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select Input; CS# must be driven high when the chip is not selected and must not be left floating at any time after power is on. |
| 2 | SO (IO1) | bidirectional | Data Output (Data Input Output 1) that serves as the serial data output in standard SPI and as IO1 in Dual/Quad SPI modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect Input (Data Input Output 2) that serves as the write-protect control input and as IO2 in Quad SPI mode. |
| 4 | VSS | power_in | Ground reference pin for the device. |
| 5 | SI (IO0) | bidirectional | Data Input (Data Input Output 0) that serves as the serial data input in standard SPI and as IO0 in Dual/Quad SPI modes. |
| 6 | SCLK | input | Serial Clock Input that times all data transfers on the serial interface. |
| 7 | HOLD# (IO3) | bidirectional | Hold Input (Data Input Output 3) that pauses serial communication and as IO3 in Quad SPI mode. |
| 8 | VCC | power_in | Power Supply pin; single supply range stated as 2.7 to 3.6 V in the features section. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | SOP-8-208mil |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature | -40 | 85 | ℃ | 41 | |||
| Storage Temperature | -65 | 150 | ℃ | 41 | |||
| Applied Input/Output Voltage | -0.6 | V | 41 | ||||
| Transient Input / Output Voltage | -2 | V | 41 | ||||
| VCC Supply Voltage (absolute maximum ratings) | VCC | -0.6 | V | 41 | |||
| Supply Voltage | VCC | 2.7 | 3.6 | V | Single power supply, full voltage range | 4 | |
| VCC(min) To CS# Low | tVSL | 5 | ms | 41 | |||
| Write Inhibit Voltage | VWI | 1.5 | 2.5 | V | 41 | ||
| Input Leakage Current | ILI | -2 | 2 | μA | 43 | ||
| Output Leakage Current | ILO | -2 | 2 | μA | 43 | ||
| Standby Current | ICC1 | 1 | 5 | μA | CS#=VCC, VIN=VCC or VSS | 43 | |
| Deep Power-Down Current | ICC2 | 1 | 5 | μA | CS#=VCC, VIN=VCC or VSS | 43 | |
| Operating Current (Read) | ICC3 | 15 | 20 | mA | CLK=0.1VCC / 0.9VCC at 120MHz, Q=Open(*1,*2,*4 I/O) | 43 | |
| Operating Current (Read) | ICC3 | 13 | 18 | mA | CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) | 43 | |
| Operating Current (PP) | ICC4 | 20 | mA | CS#=VCC | 43 | ||
| Operating Current(WRSR) | ICC5 | 20 | mA | CS#=VCC | 43 | ||
| Operating Current (SE) | ICC6 | 20 | mA | CS#=VCC | 43 | ||
| Operating Current (BE) | ICC7 | 20 | mA | CS#=VCC | 43 | ||
| Operating Current (CE) | ICC8 | 20 | mA | CS#=VCC | 43 | ||
| High Performance Current | ICC9 | 400 | 800 | uA | 43 | ||
| Output Low Voltage | VOL | 0.2 | V | IOL =100uA | 43 | ||
| Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O Without High Performance Mode), on 3.0V-3.6V power supply | fC | 104 | MHz | 3.0V-3.6V power supply | 44 | ||
| Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O Without High Performance Mode), on 2.7V-3.0V power supply | fC1 | 80 | MHz | 2.7V-3.0V power supply | 44 | ||
| Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O With High Performance Mode), on 2.7V-3.6V power supply | fC2 | 120 | MHz | With High Performance Mode, 2.7V-3.6V power supply | 44 | ||
| Serial Clock Frequency For: Fast Read (0BH), Write Status Register (01H) with or without High Performance Mode on 2.7V-3.6V power supply | fC3 | 120 | MHz | 2.7V-3.6V power supply | 44 | ||
| Serial Clock Frequency For: Read(03H) Read ID (90H, 9FH and ABH), Read Status Register (05H and 35H) | fR | 80 | MHz | 44 | |||
| Serial Clock High Time | tCLH | 4 | ns | 44 | |||
| Serial Clock Low Time | tCLL | 4 | ns | 44 | |||
| Serial Clock Rise Time (Slew Rate) | tCLCH | 0.1 | V/ns | 44 | |||
| Serial Clock Fall Time (Slew Rate) | tCHCL | 0.1 | V/ns | 44 | |||
| CS# Active Setup Time | tSLCH | 5 | ns | 44 | |||
| CS# Active Hold Time | tCHSH | 5 | ns | 44 | |||
| CS# Not Active Setup Time | tSHCH | 5 | ns | 44 | |||
| CS# Not Active Hold Time | tCHSL | 5 | ns | 44 | |||
| CS# High Time (read/write) | tSHSL | 20 | ns | 44 | |||
| Output Disable Time | tSHQZ | 6 | ns | 44 | |||
| Output Hold Time | tCLQX | 1.2 | ns | 44 | |||
| Data In Setup Time | tDVCH | 2 | ns | 44 | |||
| Data In Hold Time | tCHDX | 2 | ns | 44 | |||
| HOLD# Low Setup Time (relative to Clock) | tHLCH | 5 | ns | 44 | |||
| HOLD# High Setup Time (relative to Clock) | tHHCH | 5 | ns | 44 | |||
| HOLD# High Hold Time (relative to Clock) | tCHHL | 5 | ns | 44 | |||
| HOLD# Low Hold Time (relative to Clock) | tCHHH | 5 | ns | 44 | |||
| HOLD# Low To High-Z Output | tHLQZ | 6 | ns | 44 | |||
| HOLD# High To Low-Z Output | tHHQX | 6 | ns | 44 | |||
| Clock Low To Output Valid | tCLQV | 7 | ns | 44 | |||
| Write Protect Setup Time Before CS# Low | tWHSL | 20 | ns | 44 | |||
| Write Protect Hold Time After CS# High | tSHWL | 100 | ns | 44 | |||
| CS# High To Deep Power-Down Mode | tDP | 20 | μs | 44 | |||
| CS# High To Standby Mode Without Electronic Signature Read | tRES1 | 20 | μs | 44 | |||
| CS# High To Standby Mode With Electronic Signature Read | tRES2 | 20 | μs | 45 | |||
| CS# High To Next Command After Suspend | tSUS | 20 | us | 45 | |||
| CS# High To Next Command After Reset (from read) | tRST_R | 20 | us | 45 | |||
| CS# High To Next Command After Reset (from erase) | tRST_E | 12 | ms | 45 | |||
| Write Status Register Cycle Time | tW | 5 | 30 | ms | 45 | ||
| Page Programming Time | tPP | 0.6 | 2.4 | ms | 45 | ||
| Sector Erase Time (4K Bytes) | tSE | 45 | 150 | ms | Max 150 ms at <50K cycles; 300 ms at >50K & <100K cycles (note 1) | 45 | |
| Block Erase Time (32K Bytes) | tBE1 | 0.15 | 0.3 | s | Max 0.3 s at <50K cycles; 0.7 s at >50K & <100K cycles (note 2) | 45 | |
| Block Erase Time (64K Bytes) | tBE2 | 0.25 | 0.5 | s | Max 0.5 s at <50K cycles; 0.8 s at >50K & <100K cycles (note 3) | 45 | |
| Chip Erase Time (GD25Q80C) | tCE | 4 | 10 | s | 45 |
CAD (KiCad official)
- Symbol:
GD25Q80CSIG - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8-208mil (KiCad packages3D, STEP)
- 3D model files:
gd25q80csig-etched.step/gd25q80csig-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gd25q80csig.step/gd25q80csig.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice Semicon Beijing datasheet (54 pp, sha256
01de0142afede4c8, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# GD25Q80CSIG
**GigaDevice Semicon Beijing** · NOR FLASH · SOP-8-208mil
GD25Q80CSIG from GigaDevice Semicon Beijing, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select Input; CS# must be driven high when the chip is not selected and must not be left floating at any time after power is on. |
| 2 | SO (IO1) | bidirectional | Data Output (Data Input Output 1) that serves as the serial data output in standard SPI and as IO1 in Dual/Quad SPI modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect Input (Data Input Output 2) that serves as the write-protect control input and as IO2 in Quad SPI mode. |
| 4 | VSS | power_in | Ground reference pin for the device. |
| 5 | SI (IO0) | bidirectional | Data Input (Data Input Output 0) that serves as the serial data input in standard SPI and as IO0 in Dual/Quad SPI modes. |
| 6 | SCLK | input | Serial Clock Input that times all data transfers on the serial interface. |
| 7 | HOLD# (IO3) | bidirectional | Hold Input (Data Input Output 3) that pauses serial communication and as IO3 in Quad SPI mode. |
| 8 | VCC | power_in | Power Supply pin; single supply range stated as 2.7 to 3.6 V in the features section. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | SOP-8-208mil |
| Category | Memory |
| Pins | 8 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Ambient Operating Temperature | | -40 | | 85 | ℃ | | 41 |
| Storage Temperature | | -65 | | 150 | ℃ | | 41 |
| Applied Input/Output Voltage | | -0.6 | | | V | | 41 |
| Transient Input / Output Voltage | | -2 | | | V | | 41 |
| VCC Supply Voltage (absolute maximum ratings) | VCC | -0.6 | | | V | | 41 |
| Supply Voltage | VCC | 2.7 | | 3.6 | V | Single power supply, full voltage range | 4 |
| VCC(min) To CS# Low | tVSL | 5 | | | ms | | 41 |
| Write Inhibit Voltage | VWI | 1.5 | | 2.5 | V | | 41 |
| Input Leakage Current | ILI | -2 | | 2 | μA | | 43 |
| Output Leakage Current | ILO | -2 | | 2 | μA | | 43 |
| Standby Current | ICC1 | | 1 | 5 | μA | CS#=VCC, VIN=VCC or VSS | 43 |
| Deep Power-Down Current | ICC2 | | 1 | 5 | μA | CS#=VCC, VIN=VCC or VSS | 43 |
| Operating Current (Read) | ICC3 | | 15 | 20 | mA | CLK=0.1VCC / 0.9VCC at 120MHz, Q=Open(*1,*2,*4 I/O) | 43 |
| Operating Current (Read) | ICC3 | | 13 | 18 | mA | CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(*1,*2,*4 I/O) | 43 |
| Operating Current (PP) | ICC4 | | | 20 | mA | CS#=VCC | 43 |
| Operating Current(WRSR) | ICC5 | | | 20 | mA | CS#=VCC | 43 |
| Operating Current (SE) | ICC6 | | | 20 | mA | CS#=VCC | 43 |
| Operating Current (BE) | ICC7 | | | 20 | mA | CS#=VCC | 43 |
| Operating Current (CE) | ICC8 | | | 20 | mA | CS#=VCC | 43 |
| High Performance Current | ICC9 | | 400 | 800 | uA | | 43 |
| Output Low Voltage | VOL | | | 0.2 | V | IOL =100uA | 43 |
| Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O Without High Performance Mode), on 3.0V-3.6V power supply | fC | | | 104 | MHz | 3.0V-3.6V power supply | 44 |
| Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O Without High Performance Mode), on 2.7V-3.0V power supply | fC1 | | | 80 | MHz | 2.7V-3.0V power supply | 44 |
| Serial Clock Frequency For: Dual I/O(BBH), Quad I/O(EBH), Quad Output(6BH) (Dual I/O & Quad I/O With High Performance Mode), on 2.7V-3.6V power supply | fC2 | | | 120 | MHz | With High Performance Mode, 2.7V-3.6V power supply | 44 |
| Serial Clock Frequency For: Fast Read (0BH), Write Status Register (01H) with or without High Performance Mode on 2.7V-3.6V power supply | fC3 | | | 120 | MHz | 2.7V-3.6V power supply | 44 |
| Serial Clock Frequency For: Read(03H) Read ID (90H, 9FH and ABH), Read Status Register (05H and 35H) | fR | | | 80 | MHz | | 44 |
| Serial Clock High Time | tCLH | 4 | | | ns | | 44 |
| Serial Clock Low Time | tCLL | 4 | | | ns | | 44 |
| Serial Clock Rise Time (Slew Rate) | tCLCH | 0.1 | | | V/ns | | 44 |
| Serial Clock Fall Time (Slew Rate) | tCHCL | 0.1 | | | V/ns | | 44 |
| CS# Active Setup Time | tSLCH | 5 | | | ns | | 44 |
| CS# Active Hold Time | tCHSH | 5 | | | ns | | 44 |
| CS# Not Active Setup Time | tSHCH | 5 | | | ns | | 44 |
| CS# Not Active Hold Time | tCHSL | 5 | | | ns | | 44 |
| CS# High Time (read/write) | tSHSL | 20 | | | ns | | 44 |
| Output Disable Time | tSHQZ | | | 6 | ns | | 44 |
| Output Hold Time | tCLQX | 1.2 | | | ns | | 44 |
| Data In Setup Time | tDVCH | 2 | | | ns | | 44 |
| Data In Hold Time | tCHDX | 2 | | | ns | | 44 |
| HOLD# Low Setup Time (relative to Clock) | tHLCH | 5 | | | ns | | 44 |
| HOLD# High Setup Time (relative to Clock) | tHHCH | 5 | | | ns | | 44 |
| HOLD# High Hold Time (relative to Clock) | tCHHL | 5 | | | ns | | 44 |
| HOLD# Low Hold Time (relative to Clock) | tCHHH | 5 | | | ns | | 44 |
| HOLD# Low To High-Z Output | tHLQZ | | | 6 | ns | | 44 |
| HOLD# High To Low-Z Output | tHHQX | | | 6 | ns | | 44 |
| Clock Low To Output Valid | tCLQV | | | 7 | ns | | 44 |
| Write Protect Setup Time Before CS# Low | tWHSL | 20 | | | ns | | 44 |
| Write Protect Hold Time After CS# High | tSHWL | 100 | | | ns | | 44 |
| CS# High To Deep Power-Down Mode | tDP | 20 | | | μs | | 44 |
| CS# High To Standby Mode Without Electronic Signature Read | tRES1 | 20 | | | μs | | 44 |
| CS# High To Standby Mode With Electronic Signature Read | tRES2 | 20 | | | μs | | 45 |
| CS# High To Next Command After Suspend | tSUS | | | 20 | us | | 45 |
| CS# High To Next Command After Reset (from read) | tRST_R | 20 | | | us | | 45 |
| CS# High To Next Command After Reset (from erase) | tRST_E | 12 | | | ms | | 45 |
| Write Status Register Cycle Time | tW | | 5 | 30 | ms | | 45 |
| Page Programming Time | tPP | | 0.6 | 2.4 | ms | | 45 |
| Sector Erase Time (4K Bytes) | tSE | | 45 | 150 | ms | Max 150 ms at <50K cycles; 300 ms at >50K & <100K cycles (note 1) | 45 |
| Block Erase Time (32K Bytes) | tBE1 | | 0.15 | 0.3 | s | Max 0.3 s at <50K cycles; 0.7 s at >50K & <100K cycles (note 2) | 45 |
| Block Erase Time (64K Bytes) | tBE2 | | 0.25 | 0.5 | s | Max 0.5 s at <50K cycles; 0.8 s at >50K & <100K cycles (note 3) | 45 |
| Chip Erase Time (GD25Q80C) | tCE | | 4 | 10 | s | | 45 |
## CAD (KiCad official)
- Symbol: `GD25Q80CSIG`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8-208mil (KiCad packages3D, STEP)
- 3D model files: `gd25q80csig-etched.step` / `gd25q80csig-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd25q80csig.step` / `gd25q80csig.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588882161177145344) (54 pp, sha256 `01de0142afede4c8`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/gd25q80csig-datasheet.pdf)