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GD25Q40ETIGR

Public Made by Adom

by adom

GigaDevice Semicon Beijing NOR FLASH, SOP-8-150mil. Datasheet-verified pinout, KiCad symbol/footprint/3D.

componentmemorygd25q40etigr
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3D Model

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Symbol & Footprint

Schematic Symbol

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PCB Footprint

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Datasheet

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Contents

README

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GD25Q40ETIGR

GigaDevice Semicon Beijing · NOR FLASH · SOP-8-150mil

GD25Q40ETIGR from GigaDevice Semicon Beijing, in a SOP-8-150mil. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip Select input, active low. Must be driven high when the device is not selected; do not leave CS# floating after power-on. Enables/disables the SPI interface and terminates command sequences on rising edge.
2 SO/IO1 bidirectional Serial Data Output in standard SPI mode; becomes bidirectional data line IO1 in Dual/Quad SPI mode. Data shifts out on falling edge of SCLK.
3 WP#/IO2 bidirectional Write Protect input, active low, protects Block Protect bits (BP4-BP0) and SRP bits when low. In Quad SPI mode (QE=1 in Status Register), this pin becomes bidirectional data line IO2.
4 VSS power_in Ground reference for all signals and supply currents. Connect to system ground.
5 SI/IO0 bidirectional Serial Data Input in standard SPI mode; becomes bidirectional data line IO0 in Dual/Quad SPI mode. Input data is latched on rising edge of SCLK.
6 SCLK input Serial Clock input. Provides the timing reference for all serial input/output operations. Supports SPI modes 0 and 3, up to 133MHz for fast-read commands.
7 HOLD#/IO3 bidirectional Hold input, active low, pauses serial communication without deselecting the device when QE=0. In Quad SPI mode (QE=1), this pin becomes bidirectional data line IO3 and the HOLD function is disabled.
8 VCC power_in Power supply input, 2.7V to 3.6V single-supply operation. Decouple with local bypass capacitors to VSS.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package SOP-8-150mil
Category Memory
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • GD25Q40ETIGR
  • GD25Q40ETIGRSIGR
  • GD25Q40ETIGRSIG
  • GD25Q40ETIGRUIGR
  • GD25Q40ETIGRUIG
  • GD25Q40ETIGRWIGR
  • GD25Q40ETIGRWIG

CAD (KiCad official)

  • Symbol: GD25Q40ETIGR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-150mil (KiCad packages3D, STEP)
  • 3D model files: gd25q40etigr-etched.step / gd25q40etigr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd25q40etigr.step / gd25q40etigr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (58 pp, sha256 e2b3f327af680045, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF