main
Ray gd25q32esigr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding) 2cca7e7
{
  "schema_version": 1,
  "type": "component",
  "slug": "gd25q32esigr",
  "title": "GD25Q32ESIGR",
  "brief": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
  "version": "0.2.0",
  "license": "CC-BY-SA-4.0",
  "tags": [
    "component",
    "memory",
    "gd25q32esigr"
  ],
  "component": {
    "mpn": "GD25Q32ESIGR",
    "manufacturer": "GigaDevice Semicon Beijing",
    "package": "SOP-8-208mil",
    "pin_count": 8,
    "category": "Memory",
    "subcategory": "NOR FLASH",
    "datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2105241445_GigaDevice-Semicon-Beijing-GD25Q32ESIGR_C2832998.pdf",
    "parts": {
      "symbol": "gd25q32esigr.kicad_sym",
      "footprint": "gd25q32esigr.kicad_mod",
      "model_3d": "gd25q32esigr-etched.glb",
      "model_3d_plain": "gd25q32esigr.glb",
      "model_3d_step": "gd25q32esigr-etched.step",
      "model_3d_step_plain": "gd25q32esigr.step",
      "lbr": "gd25q32esigr.lbr"
    },
    "distributor_links": {
      "lcsc": "C2832998"
    },
    "pins": [
      {
        "number": "1",
        "name": "CS#",
        "type": "input",
        "description": "Chip Select input, active low. Must be driven high when the device is not selected; must not be left floating after power-on. Enables SPI communication and controls entry/exit of low-power/deselect states."
      },
      {
        "number": "2",
        "name": "SO(IO1)",
        "type": "bidirectional",
        "description": "Serial Data Output in Standard SPI mode (SO). Becomes bidirectional data line IO1 in Dual/Quad SPI modes. Data is shifted out on the falling edge of SCLK."
      },
      {
        "number": "3",
        "name": "WP#(IO2)",
        "type": "bidirectional",
        "description": "Write Protect input, active low, in Standard/Dual SPI modes; protects the Status Register Block Protect and SRP bits. Becomes bidirectional data line IO2 when Quad Enable (QE) bit in the Status Register is set to 1."
      },
      {
        "number": "4",
        "name": "VSS",
        "type": "power_in",
        "description": "Ground reference for the device (0V)."
      },
      {
        "number": "5",
        "name": "SI(IO0)",
        "type": "bidirectional",
        "description": "Serial Data Input in Standard SPI mode (SI). Becomes bidirectional data line IO0 in Dual/Quad SPI modes. Input data is latched on the rising edge of SCLK."
      },
      {
        "number": "6",
        "name": "SCLK",
        "type": "input",
        "description": "Serial Clock input. Provides the clock reference for all SPI transactions; SPI mode 0 and mode 3 are supported. Rated up to 133MHz (VCC=3.0-3.6V, 30pF load)."
      },
      {
        "number": "7",
        "name": "HOLD#(IO3)",
        "type": "bidirectional",
        "description": "Hold input, active low, in Standard/Dual SPI modes; pauses serial communication without deselecting the device. Becomes bidirectional data line IO3 when Quad Enable (QE) bit in the Status Register is set to 1."
      },
      {
        "number": "8",
        "name": "VCC",
        "type": "power_in",
        "description": "Single power supply input. Operating range 2.7V to 3.6V. Decouple with a local bypass capacitor near the pin."
      }
    ],
    "provenance": {
      "extractor": "ds2sf",
      "datasheet": {
        "url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2105241445_GigaDevice-Semicon-Beijing-GD25Q32ESIGR_C2832998.pdf",
        "pages": 59,
        "sha256": "f7b7ab327ffd9a02",
        "source_tier": "lcsc"
      },
      "cad": "KiCad official (CC-BY-SA 4.0)",
      "pins": {
        "total": 8,
        "described": 8,
        "cites_pages": true,
        "refuses_to_fabricate": true
      }
    },
    "viewers": {
      "symbol": "viewers/symbol.html",
      "footprint": "viewers/footprint.html"
    },
    "pin1": {
      "pad": "1",
      "at": [
        -2.475,
        -1.905
      ],
      "corner": "top-left",
      "source": "silk-marker",
      "derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
      "mark": "drawn"
    },
    "models_3d": [
      {
        "file": "gd25q32esigr.step",
        "role": "plain",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      },
      {
        "file": "gd25q32esigr-etched.step",
        "role": "eda",
        "up": "Z",
        "units": "mm",
        "origin": "footprint origin = pad-pattern centre",
        "seat": "z = 0",
        "extents_mm": [
          6,
          4.9,
          1.75
        ],
        "zmin_mm": 0,
        "centre_offset_mm": 0,
        "footprint_binding": "identity",
        "sha256": "8625933227197a0b8263f3c9ba1534bd333c753f280f394dee7683be8a4f49c0",
        "checked": "2026-10-07",
        "checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
      }
    ]
  },
  "metadata": {
    "specs": {
      "Manufacturer": "GigaDevice Semicon Beijing",
      "Package": "SOP-8-208mil",
      "Category": "Memory",
      "Pins": "8"
    }
  },
  "sections": [
    "hero",
    "viewers",
    "readme",
    "breadcrumbs",
    "info"
  ],
  "discovery_triggers": [
    "gd25q32esigr"
  ],
  "discovery_pitch": "GD25Q32ESIGR (GigaDevice Semicon Beijing) component page with datasheet-verified CAD.",
  "author": {
    "name": "Ray"
  },
  "dependencies": {},
  "hero": {
    "type": "image",
    "path": "docs/hero.png"
  },
  "files": [
    "page.json",
    "README.md",
    "gd25q32esigr.kicad_sym",
    "gd25q32esigr.kicad_mod",
    "gd25q32esigr.glb",
    "gd25q32esigr.step",
    "gd25q32esigr-etched.step",
    "gd25q32esigr.lbr",
    "docs/hero.png",
    "docs/gd25q32esigr-datasheet.pdf",
    "viewers/symbol.html",
    "viewers/footprint.html"
  ],
  "visibility": {
    "public": true
  },
  "variants": [
    {
      "mpn": "GD25Q32ESIGR",
      "kind": "packaging"
    },
    {
      "mpn": "GD25Q32ESIGRTIGR",
      "kind": "packaging"
    }
  ],
  "updated_at": "2026-09-24T20:58:11.138Z"
}