component
GD25Q32EEIGR
Public Made by Adomby adom
GigaDevice Semicon Beijing NOR FLASH, USON-8-EP(2x3). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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GD25Q32EEIGR
GigaDevice Semicon Beijing · NOR FLASH · USON-8-EP(2x3)
GD25Q32EEIGR from GigaDevice Semicon Beijing, in a USON-8-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select Input; must be driven high when chip is not selected and must not be left floating. |
| 2 | SO (IO1) | bidirectional | Serial Data Output in standard SPI mode; becomes Data Input Output 1 in Dual and Quad SPI modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect Input; must be driven high if unused or requires external pull-up resistor; acts as Data Input Output 2 in Quad SPI mode. |
| 4 | VSS | power_in | Ground. |
| 5 | SI (IO0) | bidirectional | Serial Data Input in standard SPI mode; becomes Data Input Output 0 in Dual and Quad SPI modes. |
| 6 | SCLK | input | Serial Clock Input. |
| 7 | HOLD# (IO3) | bidirectional | Hold Input; must be driven high if unused or requires external pull-up resistor; acts as Data Input Output 3 in Quad SPI mode. |
| 8 | VCC | power_in | Power Supply; 2.7-3.6V operating range. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | USON-8-EP(2x3) |
| Category | Memory |
| Pins | 9 |
CAD (KiCad official)
- Symbol:
GD25Q32EEIGR - Footprint:
Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm - 3D model: USON-8-EP(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
gd25q32eeigr-etched.step/gd25q32eeigr-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gd25q32eeigr.step/gd25q32eeigr.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GigaDevice Semicon Beijing datasheet (60 pp, sha256
4eda438f26bc9bdd, retrieved 2026-10-01, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.2, primaryclaude-haiku-4-5-20251001(text), consensusclaude-sonnet-4-6(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# GD25Q32EEIGR
**GigaDevice Semicon Beijing** · NOR FLASH · USON-8-EP(2x3)
GD25Q32EEIGR from GigaDevice Semicon Beijing, in a USON-8-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | CS# | input | Chip Select Input; must be driven high when chip is not selected and must not be left floating. |
| 2 | SO (IO1) | bidirectional | Serial Data Output in standard SPI mode; becomes Data Input Output 1 in Dual and Quad SPI modes. |
| 3 | WP# (IO2) | bidirectional | Write Protect Input; must be driven high if unused or requires external pull-up resistor; acts as Data Input Output 2 in Quad SPI mode. |
| 4 | VSS | power_in | Ground. |
| 5 | SI (IO0) | bidirectional | Serial Data Input in standard SPI mode; becomes Data Input Output 0 in Dual and Quad SPI modes. |
| 6 | SCLK | input | Serial Clock Input. |
| 7 | HOLD# (IO3) | bidirectional | Hold Input; must be driven high if unused or requires external pull-up resistor; acts as Data Input Output 3 in Quad SPI mode. |
| 8 | VCC | power_in | Power Supply; 2.7-3.6V operating range. |
| 9 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GigaDevice Semicon Beijing |
| Package | USON-8-EP(2x3) |
| Category | Memory |
| Pins | 9 |
## CAD (KiCad official)
- Symbol: `GD25Q32EEIGR`
- Footprint: `Package_SON:SON-8-1EP_3x2mm_P0.5mm_EP1.4x1.6mm`
- 3D model: USON-8-EP(2x3), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files: `gd25q32eeigr-etched.step` / `gd25q32eeigr-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `gd25q32eeigr.step` / `gd25q32eeigr.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [GigaDevice Semicon Beijing datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8590902915789758464) (60 pp, sha256 `4eda438f26bc9bdd`, retrieved 2026-10-01, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.2`, primary `claude-haiku-4-5-20251001` (text), consensus `claude-sonnet-4-6` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/gd25q32eeigr-datasheet.pdf)