component
GD25Q128ESIGR
Public Made by Adomby adom
GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
main
Ray
gd25q128esigr: component.models_3d pose record per STEP (Z-up, seated z=0, pad-centre origin, identity binding)
87c446c
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{
"schema_version": 1,
"type": "component",
"slug": "gd25q128esigr",
"title": "GD25Q128ESIGR",
"brief": "GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.",
"version": "0.2.0",
"license": "CC-BY-SA-4.0",
"tags": [
"component",
"memory",
"gd25q128esigr"
],
"component": {
"mpn": "GD25Q128ESIGR",
"manufacturer": "GigaDevice Semicon Beijing",
"package": "SOP-8-208mil",
"pin_count": 8,
"category": "Memory",
"subcategory": "NOR FLASH",
"datasheet": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2201121400_GigaDevice-Semicon-Beijing-GD25Q128ESIGR_C2928891.pdf",
"parts": {
"symbol": "gd25q128esigr.kicad_sym",
"footprint": "gd25q128esigr.kicad_mod",
"model_3d": "gd25q128esigr-etched.glb",
"model_3d_plain": "gd25q128esigr.glb",
"model_3d_step": "gd25q128esigr-etched.step",
"model_3d_step_plain": "gd25q128esigr.step",
"lbr": "gd25q128esigr.lbr"
},
"distributor_links": {
"lcsc": "C2928891"
},
"pins": [
{
"number": "1",
"name": "CS#",
"type": "input",
"description": "Chip Select input (active low). Must be driven high when chip is not selected; do not leave floating after power-on. Enables/disables the device for SPI communication."
},
{
"number": "2",
"name": "SO/IO1",
"type": "bidirectional",
"description": "Serial Data Output in standard SPI mode. Becomes bidirectional Data I/O1 when using Dual or Quad SPI commands."
},
{
"number": "3",
"name": "WP#/IO2",
"type": "bidirectional",
"description": "Write Protect input (active low) in standard/Dual SPI modes; protects Block Protect (BP4-BP0) and SRP status register bits when driven low. Becomes bidirectional Data I/O2 in Quad SPI modes (requires QE=1 in status register)."
},
{
"number": "4",
"name": "VSS",
"type": "power_in",
"description": "Ground reference (0 V) for all supplies and signals."
},
{
"number": "5",
"name": "SI/IO0",
"type": "bidirectional",
"description": "Serial Data Input in standard SPI mode. Becomes bidirectional Data I/O0 when using Dual or Quad SPI commands."
},
{
"number": "6",
"name": "SCLK",
"type": "input",
"description": "Serial Clock input. Provides the timing reference for all serial input/output operations. Supports up to 133MHz."
},
{
"number": "7",
"name": "HOLD#/RESET#/IO3",
"type": "bidirectional",
"description": "Multifunction pin acting as HOLD# (when HOLD/RST status bit = 0) or hardware RESET# (when HOLD/RST = 1) in standard/Dual SPI. Becomes bidirectional Data I/O3 in Quad SPI (when QE=1). RESET# requires low pulse ≥ tRLRH (1µs) to reset the flash."
},
{
"number": "8",
"name": "VCC",
"type": "power_in",
"description": "Main power supply. Operating range 2.7 V to 3.6 V. Bypass with a decoupling capacitor to VSS."
}
],
"provenance": {
"extractor": "ds2sf",
"datasheet": {
"url": "https://wmsc.lcsc.com/wmsc/upload/file/pdf/v2/lcsc/2201121400_GigaDevice-Semicon-Beijing-GD25Q128ESIGR_C2928891.pdf",
"pages": 63,
"sha256": "54cb85133a09da0c",
"source_tier": "lcsc"
},
"cad": "KiCad official (CC-BY-SA 4.0)",
"pins": {
"total": 8,
"described": 8,
"cites_pages": true,
"refuses_to_fabricate": true
}
},
"viewers": {
"symbol": "viewers/symbol.html",
"footprint": "viewers/footprint.html"
},
"pin1": {
"pad": "1",
"at": [
-2.475,
-1.905
],
"corner": "top-left",
"source": "silk-marker",
"derived_from": "SOIC-8_3.9x4.9mm_P1.27mm@sha256:074ecb2092b24fa4",
"mark": "drawn"
},
"models_3d": [
{
"file": "gd25q128esigr.step",
"role": "plain",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "07f46cff378d30e6c27dfd5a03092c795323f86d91c71fc7e743f4f418dc553a",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
},
{
"file": "gd25q128esigr-etched.step",
"role": "eda",
"up": "Z",
"units": "mm",
"origin": "footprint origin = pad-pattern centre",
"seat": "z = 0",
"extents_mm": [
6,
4.9,
1.75
],
"zmin_mm": 0,
"centre_offset_mm": 0,
"footprint_binding": "identity",
"sha256": "a28659e37a629590d483cb09aa1edc71e8ca71ed4f04e9d39e385c3930e9bfd5",
"checked": "2026-10-07",
"checked_by": "factory/step_pose.py (Z-up, origin, seat, binding)"
}
]
},
"metadata": {
"specs": {
"Manufacturer": "Unknown",
"Package": "SOP-8-208mil",
"Category": "Memory",
"Pins": "8"
}
},
"sections": [
"hero",
"viewers",
"readme",
"breadcrumbs",
"info"
],
"discovery_triggers": [
"gd25q128esigr"
],
"discovery_pitch": "GD25Q128ESIGR (Unknown) component page with datasheet-verified CAD.",
"author": {
"name": "Ray"
},
"dependencies": {},
"hero": {
"type": "image",
"path": "docs/hero.png"
},
"files": [
"page.json",
"README.md",
"gd25q128esigr.kicad_sym",
"gd25q128esigr.kicad_mod",
"gd25q128esigr.glb",
"gd25q128esigr.step",
"gd25q128esigr-etched.step",
"gd25q128esigr.lbr",
"docs/hero.png",
"docs/gd25q128esigr-datasheet.pdf",
"viewers/symbol.html",
"viewers/footprint.html"
],
"variants": [
{
"mpn": "GD25Q128ESIGR",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRSJG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRSEG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRFIG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRFIR",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRQIG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRWIG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRYIG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRZIG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRZIR",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRBIG",
"kind": "packaging"
},
{
"mpn": "GD25Q128ESIGRBIR",
"kind": "packaging"
}
],
"updated_at": "2026-09-24T20:57:07.474Z"
}