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GD25LQ32EEIGR

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GigaDevice Semicon Beijing NAND FLASH, USON-8-EP(2x3). Pinout extracted from the datasheet, KiCad symbol/footprint/3D.

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3D Model

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Symbol & Footprint

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Datasheet

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Contents

README

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GD25LQ32EEIGR

GigaDevice Semicon Beijing · NAND FLASH · USON-8-EP(2x3)

GD25LQ32EEIGR from GigaDevice Semicon Beijing, in a USON-8-EP(2x3). Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Active-low chip select input. Must be driven high when the device is not selected (do not leave floating after power-on). Falling edge starts an SPI transaction; rising edge terminates it and returns the device to standby.
2 SO/IO1 bidirectional Standard SPI serial data output (SO). Becomes bidirectional data line IO1 in Dual SPI, Quad SPI, and QPI modes. Data shifts out on the falling edge of SCLK.
3 WP#/IO2 bidirectional Active-low hardware write protect input when QE=0: gates the SRP/BP status-register bits so the protected memory region cannot be modified. When QE=1 (Quad SPI or QPI), this pin is repurposed as bidirectional data line IO2.
4 VSS power_in Device ground reference (0 V).
5 SI/IO0 bidirectional Standard SPI serial data input (SI). Becomes bidirectional data line IO0 in Dual SPI, Quad SPI, and QPI modes. Data is latched on the rising edge of SCLK.
6 SCLK input Serial clock input. Supports SPI mode 0 and mode 3. Up to 133 MHz for fast-read operations with 30 pF load.
7 HOLD#/IO3 bidirectional Active-low HOLD input when QE=0: pauses serial communication without deselecting the device (SO becomes high-impedance while SI/SCLK are don't-care). When QE=1 (Quad SPI or QPI), this pin is repurposed as bidirectional data line IO3.
8 VCC power_in Single-supply power input, 1.65 V to 2.0 V. Bypass locally with 100 nF to VSS. Write Inhibit Voltage (VWI) causes automatic reset if VCC drops below threshold.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package USON-8-EP(2x3)
Category Memory
Pins 8

Ordering variants

Same part, different packaging or reel option.

  • GD25LQ32EEIGR
  • GD25LQ32EEIGREFG
  • GD25LQ32EEIGRSIG
  • GD25LQ32EEIGRSFG
  • GD25LQ32EEIGRNIG
  • GD25LQ32EEIGRNFG
  • GD25LQ32EEIGRQIG
  • GD25LQ32EEIGRQFG
  • GD25LQ32EEIGRWIG
  • GD25LQ32EEIGRWFG

CAD (KiCad official)

  • Symbol: GD25LQ32EEIGR
  • Footprint: Package_SON:Winbond_USON-8-1EP_3x2mm_P0.5mm_EP0.2x1.6mm
  • 3D model: USON-8-EP(2x3) (KiCad packages3D, STEP)
  • 3D model files: gd25lq32eeigr-etched.step / gd25lq32eeigr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd25lq32eeigr.step / gd25lq32eeigr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (58 pp, sha256 eb5e3a1ad059cbf6, retrieved 2026-08-17, tier: lcsc)
  • Extractor: ds2sf (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF