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GD25LQ128ESIGR

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GigaDevice Semicon Beijing NOR FLASH, SOP-8-208mil. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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GD25LQ128ESIGR

GigaDevice Semicon Beijing · NOR FLASH · SOP-8-208mil

GD25LQ128ESIGR from GigaDevice Semicon Beijing, in a SOP-8-208mil. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 CS# input Chip Select Input; CS# must be driven high when the chip is not selected and must not be left floating at any time after power is on.
2 SO (IO1) bidirectional Data Output (Data Input Output 1), used as the IO1 data line in Dual and Quad SPI modes.
3 WP# (IO2) bidirectional Write Protect Input (Data Input Output 2), used as the IO2 data line in Quad SPI modes.
4 VSS power_in Ground.
5 SI (IO0) bidirectional Data Input (Data Input Output 0), used as the IO0 data line in Dual and Quad SPI modes.
6 SCLK input Serial Clock Input.
7 HOLD# (IO3) bidirectional Hold Input (Data Input Output 3), used as the IO3 data line in Quad SPI modes.
8 VCC power_in Power Supply; full voltage range 1.65-2.0V per the Features section.

Key specifications

Parameter Value
Manufacturer GigaDevice Semicon Beijing
Package SOP-8-208mil
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCC (min.) to device operation tVSL 2.5 ms 46
Write Inhibit Voltage VWI 1.5 V 46
Ambient Operating Temperature (TA), grade I TA -40 85 ℃ Grade I value (first of the -40 to 85 / -40 to 105 / -40 to 125 printed values) 46
Storage Temperature -65 150 ℃ 46
Transient Input/Output Voltage (overshoot) -2 V note: overshoot; upper bound printed as VCC+2.0 V 46
Applied Input/Output Voltage -0.6 V upper bound printed as VCC+0.5 V 46
VCC VCC -0.6 2.5 V 46
Supply Voltage (full voltage range) VCC 1.65 2 V 4
Input Leakage Current ILI -2 2 μA 48
Output Leakage Current ILO -2 2 μA 48
Standby Current ICC1 35 50 μA CS#=VCC, VIN=VCC or VSS 48
Deep Power-Down Current ICC2 1 10 μA CS#=VCC, VIN=VCC or VSS 48
Operating Current (Read) ICC3 15 20 mA CLK=0.1VCC / 0.9VCC at 120MHz, Q=Open(x4 I/O) 48
Operating Current (Read) ICC3 13 18 mA CLK=0.1VCC / 0.9VCC at 80MHz, Q=Open(x4 I/O) 48
Operating Current (PP) ICC4 12 20 mA CS#=VCC 48
Operating Current (WRSR) ICC5 12 20 mA CS#=VCC 48
Operating Current (SE) ICC6 12 20 mA CS#=VCC 48
Operating Current (BE) ICC7 12 20 mA CS#=VCC 48
Operating Current (CE) ICC8 12 20 mA CS#=VCC 48
Output Low Voltage VOL 0.2 V IOL = 100μA 48
Serial Clock Frequency for all commands except 03H Fc 120 MHz all commands except 03H 51
Serial Clock Frequency for 03H fR 80 MHz 03H 51
CS# Active Setup Time tSLCH 5 ns 51
CS# Active Hold Time tCHSH 5 ns 51
CS# Not Active Setup Time tSHCH 5 ns 51
CS# Not Active Hold Time tCHSL 5 ns 51
CS# High Time (Read/Write) tSHSL 20 ns 51
Output Disable Time tSHQZ 6 ns 51
Output Hold Time tCLQX 1.2 ns 51
Data In Setup Time tDVCH 2 ns 51
Data In Hold Time tCHDX 2 ns 51
HOLD# Low Setup Time (Relative To Clock) tHLCH 5 ns 51
HOLD# High Setup Time (Relative To Clock) tHHCH 5 ns 51
HOLD# Low Hold Time (Relative To Clock) tCHHH 5 ns 51
HOLD# High Hold Time (Relative To Clock) tCHHL 5 ns 51
HOLD# Low To High-Z Output tHLQZ 6 ns 51
HOLD# High To Low-Z Output tHHQX 6 ns 51
Clock Low To Output Valid tCLQV 7 ns CL = 30pF 51
Clock Low To Output Valid tCLQV 6 ns CL = 15pF 51
Write Protect Setup Time Before CS# Low tWHSL 20 ns 51
Write Protect Hold Time After CS# High tSHWL 100 ns 51
CS# High To Deep Power-Down Mode tDP 20 μs 51
CS# High To Standby Mode Without Electronic Signature Read tRES1 20 μs 51
CS# High To Standby Mode With Electronic Signature Read tRES2 20 μs 51
CS# High To Next Command After Suspend tSUS 20 μs 51
Latency Between Resume And Next Suspend tRS 100 μs 51
CS# High To Next Command After Reset (Except From Erase) tRST 30 μs 51
CS# High To Next Command After Reset (From Erase) tRST_E 12 ms 51
Write Status Register Cycle Time tW 5 30 ms 52
Byte Program Time (First Byte) tBP1 30 60 μs 52
Additional Byte Program Time (After First Byte) tBP2 2.5 5 μs 52
Page Programming Time tPP 0.5 2.4 ms 52
Sector Erase Time tSE 70 400 ms 52
Block Erase Time (32K Bytes) tBE1 0.16 0.8 s 52
Block Erase Time (64K Bytes) tBE2 0.3 1.2 s 52
Chip Erase Time (GD25LQ128E) tCE 50 120 s 52
Reset Pulse Width tRLRH 1 μs 57
Reset High Time Before Read tRHSL 50 ns 57
Reset Recovery Time tRB 12 ms 57

CAD (KiCad official)

  • Symbol: GD25LQ128ESIGR
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8-208mil (KiCad packages3D, STEP)
  • 3D model files: gd25lq128esigr-etched.step / gd25lq128esigr-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gd25lq128esigr.step / gd25lq128esigr.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: GigaDevice Semicon Beijing datasheet (70 pp, sha256 69c0a9f603ad87a9, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF