main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 2d ago
viewers gc4344: viewers · Ray 2d ago
gc4344-etched.glb Publish 0.1.0 · Ray 2d ago
gc4344-etched.step gc4344: factory component page (tier=lcsc) · Ray 2d ago
gc4344-hero.glb gc4344: hero GLB from the etched model (keeps the MPN mark) · Ray 2d ago
gc4344-hero.overlay.json Publish 0.1.0 · Ray 2d ago
gc4344.glb Publish 0.1.0 · Ray 2d ago
gc4344.kicad_mod Publish 0.1.0 · Ray 2d ago
gc4344.kicad_sym Publish 0.1.0 · Ray 2d ago
gc4344.lbr Publish 0.1.0 · Ray 2d ago
gc4344.step Publish 0.1.0 · Ray 2d ago
package.json Publish 0.1.0 · Ray 2d ago
page.json Set visibility: public · Ray 2d ago
README.md Publish 0.1.0 · Ray 2d ago
verification.json Verified: Published by the parts factory: tier lcsc, 10 pins · Ray 2d ago

GC4344

SX-globalchip · Digital To Analog Converters (DACs) · MSOP-10

GC4344 from SX-globalchip, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 SDIN input Serial audio data input; digital input voltage must stay between -0.3 V and VA+0.4 V, with VA recommended at 3 V to 5.5 V.
2 DEM /SCLK input External serial clock input port; holding it low for five consecutive LRCK falling edges starts the de-emphasis filter, which is only valid in internal serial clock mode.
3 LRCK input Left/right clock port that determines the channel of the current input data, with a frequency equal to the input sample rate Fs and synchronized with SCLK.
4 MCLK input Primary master clock port, where the MCLK/LRCK ratio must be an integer and MCLK is specified at 0.512 MHz to 50 MHz with a 45% to 55% duty cycle.
5 VQ passive Filter connection for the internal quiescent voltage, which is specified as 0.5•VA VDC.
6 FILT+ passive Positive reference voltage for the internal sampling circuits.
7 AOUTL output Analog left channel output with a full-scale output of 0.60•VA to 0.70•VA Vpp, a maximum DC current of 10 uA, and a maximum load capacitance of 100 pF.
8 GND power_in Ground.
9 VA power_in Analog power supply with an absolute maximum of 6.0 V and a recommended range of 3 V to 5.5 V.
10 AOUTR output Analog right channel output with a full-scale output of 0.60•VA to 0.70•VA Vpp, a maximum DC current of 10 uA, and a maximum load capacitance of 100 pF.

Key specifications

Parameter Value
Manufacturer SX-globalchip
Package MSOP-10
Category ADC/DAC/Data Conversion
Pins 10

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VA (absolute maximum rating; min column) VA -0.3 6 V Recommended scope 3V-5.5V 2
Input current, any pin except supplies -10 10 mA Any pin except supplies; printed as ±10 mA 2
Digital input voltage -0.3 V Recommended scope 3V-5.5V; max printed as VA+0.4 V (not numeric) 2
Operating temperature (absolute) -55 125 ºC 2
Storage temperature -65 150 ºC 2
Supply voltage VA (recommended) VA 3 5.5 V Recommended scope 3V-5.5V 2
Operating temperature (recommended) -40 85 ºC 2
Dynamic range, 18 to 24-bit A-weighted 99 105 dB Full-scale 997 Hz, Fs=48/96/192 kHz; 5 V column 3
Dynamic range, 18 to 24-bit A-weighted 97 103 dB Full-scale 997 Hz, Fs=48/96/192 kHz; 3.3 V column 3
Dynamic range, 18 to 24-bit unweighted 96 102 dB Full-scale 997 Hz, Fs=48/96/192 kHz; 5 V column 3
Dynamic range, 18 to 24-bit unweighted 94 100 dB Full-scale 997 Hz, Fs=48/96/192 kHz; 3.3 V column 3
Dynamic range, 16-bit A-weighted 90 96 dB Full-scale 997 Hz, Fs=48/96/192 kHz; 5 V column 3
Dynamic range, 16-bit unweighted 87 93 dB Full-scale 997 Hz, Fs=48/96/192 kHz; 5 V column 3
THD+N, 18 to 24-bit at -20 dB -82 -76 dB 5 V column 3
THD+N, 18 to 24-bit at -20 dB -80 -74 dB 3.3 V column 3
THD+N, 18 to 24-bit at -60 dB -42 -36 dB 5 V column 3
THD+N, 18 to 24-bit at -60 dB -40 -34 dB 3.3 V column 3
THD+N, 16-bit at -20 dB -73 -67 dB 5 V column 3
THD+N, 16-bit at -60 dB -33 -27 dB 5 V column 3
Interchannel gain mismatch 0.1 0.25 dB 3
Passband to -0.1 dB corner 0 0.35 fs Single-speed mode 3
Passband to -3 dB corner 0 0.499 fs Single-speed mode 3
Frequency response -0.175 0.1 dB Single-speed mode; 10 Hz to 20 kHz 3
StopBand 0.5465 fs Single-speed mode 3
StopBand attenuation 50 dB Single-speed mode 3
Passband to -0.1 dB corner 0 0.22 fs Double-speed mode 3
Passband to -3 dB corner 0 0.501 fs Double-speed mode 3
Frequency response -0.15 0.15 dB Double-speed mode; 10 Hz to 20 kHz 3
StopBand 0.577 fs Double-speed mode 3
StopBand attenuation 55 dB Double-speed mode 3
Passband to -0.1 dB corner 0 0.11 fs Quad-speed mode 3
Passband to -3 dB corner 0 0.469 fs Quad-speed mode 3
Frequency response -0.12 0 dB Quad-speed mode; 10 Hz to 20 kHz 3
StopBand 0.7 fs Quad-speed mode 3
StopBand attenuation 51 dB Quad-speed mode 3
Input leakage current Iin -10 10 uA Printed as ±10 uA 4
Normal operation supply current (5 V) IA 21 30 mA Normal operation, 5 V 4
Normal operation supply current (3.3 V) 15 20 mA Normal operation, 3.3 V 4
MCLK frequency 0.512 50 MHz 4
MCLK duty cycle 45 55 % MCLK frequency input 4
Input sample rate fs fs 2 200 KHz All MCLK/LRCK ratios combined 4
Input sample rate fs 84 134 KHz 256x, 384x MCLK/LRCK ratio 4
Input sample rate fs 42 67 KHz 512x, 768x MCLK/LRCK ratio 4
Input sample rate fs 30 34 KHz 1152x MCLK/LRCK ratio 4
Input sample rate fs 50 100 KHz 128x, 192x MCLK/LRCK ratio 4
Input sample rate fs 100 200 KHz 64x, 96x MCLK/LRCK ratio 4
Input sample rate fs 168 200 KHz 128x, 192x MCLK/LRCK ratio 4
LRCK duty cycle (external SCLK only) 45 50 55 % External SCLK mode 4
SCLK pulse width low tsclkl 20 ns External SCLK mode 4
SCLK pulse width high tsclkh 20 ns External SCLK mode 4
SCLK duty cycle 45 50 55 % External SCLK mode 4
SCLK rising to LRCK edge delay tslrd 20 ns External SCLK mode 4
SCLK rising to LRCK edge setup time tslrs 20 ns External SCLK mode 4
SDIN valid to SCLK rising setup time tsdlrs 20 ns External SCLK mode 4
SCLK rising to SDIN hold time tsdh 20 ns External SCLK mode 4

CAD (KiCad official)

  • Symbol: GC4344
  • Footprint: Package_SO:MSOP-10_3x3mm_P0.5mm
  • 3D model: MSOP-10 (KiCad packages3D, STEP)
  • 3D model files: gc4344-etched.step / gc4344-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gc4344.step / gc4344.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: SX-globalchip datasheet (10 pp, sha256 7c8267d8b6abd962, retrieved 2026-11-05, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF