GC1808 from SX-globalchip, in a TSSOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	VREF	power_in	Reference voltage decoupling pin; the central voltage VREF is 0.5 VCC per the datasheet.
2	AGND	power_in	Analog ground, referenced to 0 V with a tolerance of ±0.1 V relative to DGND.
3	VCC	power_in	Analog supply, recommended 4.5 V to 5.5 V (typical 5 V) with an absolute maximum of 6.5 V.
4	VDD	power_in	Digital supply, recommended 2.7 V to 3.6 V (typical 3.3 V) with an absolute maximum of 4 V.
5	DGND	power_in	Digital ground, referenced to 0 V with a tolerance of ±0.1 V relative to AGND.
6	SCKI	input	System clock input at 256 fS, 384 fS or 512 fS, with a range of 2.048 MHz to 49.152 MHz.
7	LRCK	bidirectional	Audio data latch enable (word clock), an output in master mode and an input in slave mode that must be synchronous with SCKI.
8	BCK	bidirectional	Audio bit clock, an output in master mode with 64 BCK per frame and an input in slave mode.
9	DOUT	output	Digital audio data output, with a specified load capacitance of 20 pF maximum in the recommended conditions.
10	MD0	input	Audio interface mode select 0, which together with MD1 selects master or slave mode and must be set before power-up.
11	MD1	input	Audio interface mode select 1, which together with MD0 selects master or slave mode and must be set before power-up.
12	FMT	input	Audio format select that switches between I2S and left-justified data formats, controllable by external GPIO or pull-up/pull-down resistors.
13	VINL	input	Analog left channel input, single-ended with 3 Vp-p full scale at VCC = 5 V and an input impedance of 60 kΩ.
14	VINR	input	Analog right channel input, single-ended with 3 Vp-p full scale at VCC = 5 V and an input impedance of 60 kΩ.

Key specifications

Parameter	Value
Manufacturer	SX-globalchip
Package	TSSOP-14
Category	ADC/DAC/Data Conversion
Pins	14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Analog supply voltage VCC	VCC	4.5	5	5.5	V		4
Digital supply voltage VDD	VDD	2.7	3.3	3.6	V		4
System clock frequency		2.048		49.152	MHz		4
Digital sampling clock	fS	8		96	kHz		4
Analog supply voltage VCC absolute	VCC	-0.3	5	6.5	V		4
Digital supply voltage VDD absolute	VDD	-0.3	3.3	4	V		4
Digital input voltage SCKI, MD0, MD1, FMT		-0.3		6.5	V		4
Operating temperature TA (commercial grade)	TA	-10		70	C	commercial grade	4
ESD HBM		-4000		4000	V	HBM	4
Sampling frequency fS	fS	8	48	96	kHz		5
System clock frequency 256 fS		2.048	12.288	24.576	MHz	256 fS	5
System clock frequency 384 fS		3.072	18.432	36.864	MHz	384 fS	5
System clock frequency 512 fS		4.096	24.576	49.152	MHz	512 fS	5
Digital logic input low VIL	VIL	0		0.8	VDC		5
Analog logic input high VIH	VIH	2		5.5	VDC		5
Analog logic input low VIL	VIL	0		0.8	VDC		5
Digital high-level input current IIH	IIH	-10		10	µA	VIN = VDD	5
Digital low-level input current IIL	IIL	-10		10	µA	V = 0 V	5
Analog high-level input current IIH	IIH		65	100	µA	VIN = VDD	5
Analog low-level input current IIL	IIL	-10		10	µA	VIN = 0 V	5
Logic output high VOH	VOH	2.8			VDC	IOUT=-4mA	5
Logic output low VOL	VOL			0.5	VDC	IOUT = 4 mA	5
Channel gain mismatch		-3	1	3	% of FSR		5
Gain error		-6	3	6	% of FSR		5
THD+N	THD+N		-93	-87	dB	VIN=-0.5 dB, fs = 48 kHz	5
THD+N	THD+N			-87	dB	VIN=-0.5 dB, fs = 96 kHz	5
Dynamic range		95	99		dB	fs = 48 kHz, A-weighted	6
Signal-to-noise ratio S/N	S/N	95	99		dB	fs = 48 kHz, A-weighted	6
Channel isolation		93	97		dB	fs = 48 kHz	6
Digital filter passband ripple		-0.05		0.05	dB		6
Analog supply current GCC	GCC		8.6	11	mA	fs = 48kHz, 96 kHz	6
Digital supply current IDD	IDD		5.9	8	mA	fs = 48 kHz	6
System clock duty cycle		40		60	%		7
SCKI high-level time tw(SCKH)	tw(SCKH)	8			ns		7
SCKI low-level time tw(SCKL)	tw(SCKL)	8			ns		7
LRCK to BCK rising edge setup time (slave)	t(LRSU)	50			ns		7
LRCK to BCK rising edge hold time (slave)	t(LRHD)	10			ns		7
BCK falling edge to DOUT delay (slave)	t(CKDO)	-10		40	ns		7
LRCK edge to DOUT delay (slave)	t(LRDO)	-10		40	ns		7
BCK period (master)	t(BCKP)	150		2000	ns	master mode	7
BCK high-level width (master)	t(BCKH)	65		1200	ns	master mode	7
BCK low-level width (master)	t(BCKL)	65		1200	ns	master mode	7
BCK falling edge to LRCK valid (master)	t(CKLR)	-10		20	ns	master mode	7
LRCK period (master)	t(LRCP)	10		125	ns	master mode	7
BCK falling edge to DOUT delay (master)	t(CKDO)	-10		20	ns	master mode	7
LRCK edge to DOUT delay (master)	t(LRDO)	-10		20	ns	master mode	7
SCKI rising edge to BCK edge delay (master)	t(SCKBCK)	5		30	ns	master mode, BCK as output	8

CAD (KiCad official)

Symbol: GC1808
Footprint: Package_SO:TSSOP-14_4.4x5mm_P0.65mm
3D model: TSSOP-14 (KiCad packages3D, STEP)
3D model files: gc1808-etched.step / gc1808-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); gc1808.step / gc1808.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: SX-globalchip datasheet (17 pp, sha256 775a3ac8deabe157, retrieved 2026-11-05, tier: lcsc)
Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

GC1808

Verified GC1808

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3D Model

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Datasheet

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