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GBI5130QYAR
Public Made by Adomby adom
GOSEMICON Voltage Regulators - Linear, Low Drop Out (LDO) Regulators, QFN-20(3.5x3.5). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
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Datasheet
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Contents
README
markdownGBI5130QYAR
GOSEMICON · Voltage Regulators - Linear, Low Drop Out (LDO) Regulators · QFN-20(3.5x3.5)
GBI5130QYAR from GOSEMICON, in a QFN-20(3.5x3.5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OUT | power_out | Regulated output pin that requires a 22µF or larger capacitor (10µF or greater effective capacitance) for stability, placed as close to the device as possible. |
| 2 | SNS | input | Output voltage sense pin, connected only when setting VOUT through PCB layout with no external resistor, and kept floating when VOUT is set by an external resistor. |
| 3 | FB | input | Feedback pin to the error amplifier, where a 10nF feed-forward capacitor to OUT is recommended but may disrupt Power-Good functionality. |
| 4 | PG | output | Open-drain power-good output that is active high when VOUT is above 91% of target and is pulled low below 85% of target, during EN shutdown, OTP, or OCP. |
| 5 | 25mV | input | Voltage setting pin for the internal feedback network that is tied to GND to increase VOUT, tied to SNS to increase resolution, or left floating when not used. |
| 6 | 50mV | input | Voltage setting pin for the internal feedback network that is tied to GND to increase VOUT, tied to SNS to increase resolution, or left floating when not used. |
| 7 | 100mV | input | Voltage setting pin for the internal feedback network that is tied to GND to increase VOUT, tied to SNS to increase resolution, or left floating when not used. |
| 8 | GND | power_in | Ground pin that must be connected to ground, the thermal pad, and the other GND pins with a low-impedance connection. |
| 9 | 200mV | input | Voltage setting pin for the internal feedback network that is tied to GND to increase VOUT, tied to SNS to increase resolution, or left floating when not used. |
| 10 | 400mV | input | Voltage setting pin for the internal feedback network that is tied to GND to increase VOUT, tied to SNS to increase resolution, or left floating when not used. |
| 11 | 800mV | input | Voltage setting pin for the internal feedback network that is tied to GND to increase VOUT, tied to SNS to increase resolution, or left floating when not used. |
| 12 | BIAS | input | BIAS supply voltage that enables LILO operation (for example VIN=1.2V, VOUT=1V) and requires a 1µF (0.47µF minimum) capacitor to ground, or is left floating or tied to ground if unused. |
| 13 | NR/SS | bidirectional | Noise-reduction and soft-start pin where a capacitor to ground reduces reference noise and sets soft-start, with 10nF or larger recommended as close to the pin as possible. |
| 14 | EN | input | Enable pin where logic high enables the device and logic low disables it, and it must be tied to IN or BIAS if enable functionality is not required. |
| 15 | IN | power_in | Input supply pin requiring a 10µF or larger ceramic capacitor (5µF minimum capacitance) from IN to ground, placed as close as possible to the input. |
| 16 | IN | power_in | Input supply pin requiring a 10µF or larger ceramic capacitor (5µF minimum capacitance) from IN to ground, placed as close as possible to the input. |
| 17 | IN | power_in | Input supply pin requiring a 10µF or larger ceramic capacitor (5µF minimum capacitance) from IN to ground, placed as close as possible to the input. |
| 18 | GND | power_in | Ground pin that must be connected to ground, the thermal pad, and the other GND pins with a low-impedance connection. |
| 19 | OUT | power_out | Regulated output pin that requires a 22µF or larger capacitor (10µF or greater effective capacitance) for stability, placed as close to the device as possible. |
| 20 | OUT | power_out | Regulated output pin that requires a 22µF or larger capacitor (10µF or greater effective capacitance) for stability, placed as close to the device as possible. |
| 21 | THERMAL PAD | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | GOSEMICON |
| Package | QFN-20(3.5x3.5) |
| Category | Power Management (PMIC) |
| Pins | 21 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Input supply voltage range | VIN | 1.1 | 6.5 | V | 6 | ||
| Input supply voltage range (bias) | VBIAS | 3 | 6.5 | V | VIN = 1.1V | 6 | |
| Input supply UVLO with BIAS | VUVLO1(IN) | 1.02 | 1.085 | V | VIN rising with VBIAS = 3V | 6 | |
| Input supply UVLO without BIAS | VUVLO2(IN) | 1.28 | 1.39 | V | VIN rising | 6 | |
| Dropout voltage | VDO | 80 | 160 | mV | VIN = 1.4V, IOUT = 4A, VFB = 0.5V -3% | 7 | |
| Output voltage range (programming pin) | VOUT | 0.5 | 2.075 | V | Using programming pin | 7 | |
| Output voltage range (external resistors) | VOUT | 0.5 | 5.15 | V | Using external resistors | 7 | |
| Output voltage accuracy | -1 | 1 | % | 0.5V ≤ VOUT ≤ 5.15V; 5mA ≤ IOUT ≤ 4A; over VIN; -40~85℃ | 7 | ||
| Output voltage accuracy | -1.5 | 1.5 | % | 0.5V ≤ VOUT ≤ 5.15V; 5mA ≤ IOUT ≤ 4A; 3V ≤ VBIAS ≤ 6.5V; -40~125℃ | 7 | ||
| Output voltage accuracy with BIAS | -1 | 1 | % | 0.5V ≤ VOUT ≤ 5.15V; 5mA ≤ IOUT ≤ 4A; 3V ≤ VBIAS ≤ 6.5V; -40~85℃ | 7 | ||
| Output voltage accuracy with BIAS | -1.5 | 1.5 | % | 0.5V ≤ VOUT ≤ 5.15V; 5mA ≤ IOUT ≤ 4A | 7 | ||
| FB pin leakage current | IFB | -100 | 100 | nA | VIN = 6.5V | 7 | |
| NR/SS pin charging current | INR/SS | 4.5 | 6 | 7.5 | μA | VNR/SS = 0V, VIN = 6.5V | 7 |
| PG pin threshold (falling VOUT) | VPG_IT | 80 | 85 | 90 | % | For falling VOUT | 9 |
| Operating junction temperature | TJ | -40 | 125 | ℃ | 9 | ||
| Operating junction temperature | TJ | -40 | 125 | °C | 5 | ||
| Storage temperature | TSTG | -65 | 150 | °C | 5 | ||
| Voltage IN, BIAS, PG, EN | -0.3 | 7 | V | 5 | |||
| Voltage SNS, OUT | -0.3 | V | Upper limit printed as IN+0.3 V | 5 | |||
| Voltage NR/SS, FB | -0.3 | 3.6 | V | 5 | |||
| Voltage 25mV, 50mV, 100mV, 200mV, 400mV, 800mV pins | -0.3 | V | Upper limit printed as OUT+0.3 V | 5 | |||
| Current PG | 5 | mA | 5 | ||||
| Input supply voltage range | VIN | 1.1 | 6.5 | V | 5 | ||
| Bias supply voltage range | VBIAS | 3 | 6.5 | V | 5 | ||
| Output voltage range | VOUT | 0.5 | 5.15 | V | 5 | ||
| Enable voltage range | VEN | 0 | V | Upper limit printed as VIN | 5 | ||
| Output current | IOUT | 0 | 4 | A | 5 | ||
| Input capacitor | CIN | 10 | 47 | μF | 5 | ||
| Output capacitor | COUT | 47 | 100 | μF | 6 | ||
| Power-good pullup resistance | RPG | 10 | 100 | kΩ | 6 | ||
| Operating junction temperature | TJ | -40 | 125 | ℃ | 6 | ||
| Hysteresis of VUVLO1(IN) | VHYS1(IN) | 200 | mV | VBIAS = 3V | 6 | ||
| Hysteresis of VUVLO2(IN) | VHYS2(IN) | 220 | mV | 6 | |||
| Bias supply UVLO | VUVLO(BIAS) | 2.8 | V | VIN rising, VIN = 1.1V | 6 | ||
| Hysteresis of VUVLO2(BIAS) | VHYS(BIAS) | 140 | mV | 7 | |||
| EN pin low-level output voltage | VIL(EN) | 0.5 | V | 7 | |||
| EN pin high-level output voltage | VIH(EN) | 1.1 | V | 7 | |||
| PG pin low-level output voltage | VOL(PG) | 0.4 | V | IPG = 1mA | 7 | ||
| Feedback voltage | VFB | 0.5 | V | 7 | |||
| NR/SS pin voltage | VNR/SS | 0.5 | V | 7 | |||
| PG pin hysteresis | VPG_Hys | 6 | % | For rising VOUT | 9 | ||
| Shutdown current (label partly printed) | 3 | μA | Shutdown, PG open; VIN = 6.5V, VEN = 0.5V | 9 | |||
| Thermal shutdown temperature | TSD | 160 | ℃ | Shutdown, temperature increasing | 9 | ||
| Thermal shutdown reset temperature | TSD | 140 | ℃ | Reset, temperature decreasing | 9 | ||
| Bias pin capacitor | CBIAS | 10 | μF | 6 | |||
| NR/SS capacitor | CNR/SS | 10 | nF | 6 | |||
| Feed-forward capacitor | CFF | 10 | nF | 6 | |||
| Top resistor value in feedback divider | R1 | 10 | kΩ | 6 | |||
| Bottom resistor value in feedback divider | R2 | 160 | kΩ | 6 | |||
| Junction to ambient thermal resistance | RθJA | 43 | °C/W | QFN20 | 6 | ||
| Junction to case (top) thermal resistance | RθJC(top) | 38 | °C/W | QFN20 | 6 | ||
| Junction to top characterization parameter | ψJT | 0.8 | °C/W | QFN20 | 6 | ||
| Junction to board characterization parameter | ψJB | 17.5 | °C/W | QFN20 | 6 |
Materials and finish
As the datasheet states them (page.json metadata.appearance; the 3D model's colours follow it).
| Part | Material | Colour / plating | Datasheet says | Page |
|---|---|---|---|---|
| contacts | copper | output capacitor, and to the LDO ground pin as close as possible to each other, connected by a wide, component-side, copper surface. The use of vias and long traces to the input and output capacitors | 33 |
CAD (KiCad official)
- Symbol:
GBI5130QYAR - Footprint:
Package_DFN_QFN:QFN-20-1EP_3.5x3.5mm_P0.5mm_EP2x2mm - 3D model: QFN-20(3.5x3.5), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
gbi5130qyar-etched.step/gbi5130qyar-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);gbi5130qyar.step/gbi5130qyar.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: GOSEMICON datasheet (34 pp, sha256
b616a292ad948922, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).