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FXL6408UMX

Public Made by Adom

by adom

onsemi I/O Expanders, UQFN-16(1.8x2.6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FXL6408UMX

onsemi · I/O Expanders · UQFN-16(1.8x2.6)

FXL6408UMX from onsemi, in a UQFN-16(1.8x2.6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 /INT output Interrupt output, open-drain and active LOW, requires an external pull-up resistor to VCC.
2 VDDIO power_in Voltage reference for the I/O-side voltage translation, with a recommended range of 1.65 V to 4.00 V; tie to VCC if I/O translation is not needed.
3 GPIO7 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
4 GPIO6 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
5 GPIO5 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
6 GPIO4 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
7 GPIO3 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
8 GPIO2 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
9 ADDR input Address input that is tied to GND or VCC to select one of the two I2C device addresses (Table 1).
10 /RST input Reset input, active LOW, requires a pull-up resistor to VCC.
11 GPIO1 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
12 GPIO0 bidirectional General-purpose programmable I/O, referenced to VDDIO, with up to 4.0 V GPIO pin capability and 6 mA output drive.
13 SCL input I2C serial clock bus line, requires a pull-up resistor to VCC.
14 SDA bidirectional I2C serial data bus line, requires a pull-up resistor to VCC.
15 VCC power_in Device supply voltage, operating range 1.65 V to 3.60 V, and also the reference for the I2C, ADDR, /INT and /RST pins.
16 GND power_in Ground reference.

Key specifications

Parameter Value
Manufacturer onsemi
Package UQFN-16(1.8x2.6)
Category Interface
Pins 16

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltages (VCC, VDDIO) VCC, VDDIO -0.5 4.6 V 4
DC Input Voltage VIN -0.5 4 V 4
Output Voltage VOUT -0.5 4 V note 1 4
DC Input Diode Current IIK -50 mA VIN < 0 V 4
DC Output Diode Current IOK -50 mA VOUT < 0 V 4
DC Output Sink Current IOL 50 mA 4
DC VCC or Ground Current per Supply Pin ICC 100 mA per supply pin 4
Storage Temperature Range TSTG -65 150 C 4
Junction Temperature under Bias TJ 150 C under bias 4
Junction Lead Temperature, Soldering TL 260 C 10 seconds 4
Thermal Resistance, Junction-to-Ambient ΘJA 115 °C/W junction-to-ambient 4
ESD Human Body Model ESD HBM 4 kV JESD22-A114 4
ESD Charged Device Model ESD CDM 2 JESD22-C101 4
Supply Voltage Operating VCC 1.65 3.6 V Operating 4
I/O Side Reference Voltage VDDIO 1.65 4 V 4
Input Voltage on I/O pins VIN 0 4 V 4
Output Voltage VOUT 0 V max = VDDIO (printed as expression) 4
Operating Temperature TA -40 85 °C 4
Input Rise and Fall Times to I/O Pins tr, tf 0 200 ns/V VDDIO at 1.8 V, 2.5 V ±0.2 V; configured as inputs 4
Input Rise and Fall Times to I/O Pins tr, tf 0 100 ns/V VDDIO at 3.6 V ±0.3 V; configured as inputs 4
Power-On Reset Voltage VPOR 1.25 1.25 V VDDIO=0 to 4.0 V 5
Input Leakage Current (RST, ADDR, SDA, SCL, /INT) IIN -1 1 µA 0 ≤ VIN ≤ VCC; VCC 0 to 3.6 V; TA=25°C 5
Input Leakage Current (RST, ADDR, SDA, SCL, /INT) IIN -10 10 µA 0 ≤ VIN ≤ VCC; VCC 0 to 3.6 V; TA=-40 to 85°C 5
Power-Off Leakage Current IOFF 1 µA VIN or VOUT=3.6 V; VCC=0; TA=25°C 5
Power-Off Leakage Current IOFF 10 µA VIN or VOUT=3.6 V; VCC=0; TA=-40 to 85°C 5
Standby Mode Supply Current (SCL in static condition) ICC 1.2 1.5 µA VIN=VCC or GND; VCC 1.8 to 3.6 V 5
Active Mode Supply Current (SCL active) ICC 300 µA SCL active; VCC 1.8 to 3.6 V 5
Output Low Current IOL 6 mA VDDIO 1.8 to 4.0 V 5
Output High Current IOH -6 mA VDDIO 1.8 to 4.0 V 5
Input Low Current IIN -50 50 µA 0 ≤ VIN ≤ VDDIO; VDDIO 1.8 to 4.0 V; note 3 5
Power-Off Leakage Current (GPIO) IOFF 1 µA VIN=4.0 V; VDDIO=0; TA=25°C 5
Power-Off Leakage Current (GPIO) IOFF 10 µA VIN=4.0 V; VDDIO=0; TA=-40 to 85°C 5
LOW Level Output Voltage VOL 0.2 V VIN=VIL, IOL=-100 µA; VDDIO=1.8 V 5
LOW Level Output Voltage VOL 0.45 V VIN=VIL, IOL=-6 mA; VDDIO=1.8 V 5
LOW Level Output Voltage VOL 0.5 V VIN=VIL, IOL=-6 mA; VDDIO=3.6 V 5
Pull-Up or Pull-Down Resistors RPULL 100 kΩ 5
LOW-level Output Voltage (open-drain, SDA/SCL) VOL 0 0.4 V 3 mA sink current; open-drain or open-collector; VCC > 2 V 7
Input Current of Each I/O Pin II -10 10 µA input voltage 0.26 V to 2.34 V 7
Capacitance for Each I/O Pin CI 10 pF 7
SCL Clock Frequency fSCL 0 400 kHz Fast Mode (400 kHz) 7
Hold Time (Repeated) START Condition tHD;STA 0.6 µs 7
LOW Period of SCL Clock tLOW 1.3 µs note 4 7
HIGH Period of SCL Clock tHIGH 0.6 µs 7
Set Up Time for Repeated START Condition tSU;STA 0.6 µs 7
Data Hold Time tHD;DAT 0 0.9 µs see Figure 7 7
Data Set Up Time tSU;DAT 100 ns note 5 7
Set Up Time Required by SDA Input Buffer tPS 0 ns when receiving data 7
Out Delay Required by SDA Output Buffer tPH 300 ns when transmitting data 7
Rise Time of SDA and SCL Signals tr 300 ns 20+0.1Cb (notes 6, 7) 7
Fall Time of SDA and SCL Signals tf 300 ns 20+0.1Cb (notes 6, 7) 7
Set Up Time for STOP Condition tSU;STOP 0.6 µs 7
Bus Free Time between STOP and START tBUF 1.3 µs 7
Pulse Width of Spikes Suppressed by Input Filter tSP 0 50 ns 7
Reset Pulse Duration tw 150 ns see Figure 4 6
Input Glitch Rejection on RST Pin tRST_GLITCH 50 150 ns see Figure 4 6
Reset Time, rising edge of reset pulse to falling edge of /INT tRESET 150 ns see Figure 5 6
Time from Input Default State Change to /INT driven LOW tIV 4 µs see Figure 6 6

CAD (KiCad official)

  • Symbol: FXL6408UMX
  • Footprint: Package_DFN_QFN:UQFN-16_1.8x2.6mm_P0.4mm
  • 3D model: UQFN-16(1.8x2.6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.55 mm nominal UFQFPN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: fxl6408umx-etched.step / fxl6408umx-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fxl6408umx.step / fxl6408umx.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (17 pp, sha256 c3cdadb35cd08375, retrieved 2026-10-17, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF