main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 5d ago
viewers fw342-tl-e-vb: viewers · Ray 5d ago
fw342-tl-e-vb-etched.glb Publish 0.1.0 · Ray 5d ago
fw342-tl-e-vb-etched.step fw342-tl-e-vb: factory component page (tier=lcsc) · Ray 5d ago
fw342-tl-e-vb-hero.glb fw342-tl-e-vb: hero GLB from the etched model (keeps the MPN mark) · Ray 5d ago
fw342-tl-e-vb-hero.overlay.json Publish 0.1.0 · Ray 5d ago
fw342-tl-e-vb.glb Publish 0.1.0 · Ray 5d ago
fw342-tl-e-vb.kicad_mod Publish 0.1.0 · Ray 5d ago
fw342-tl-e-vb.kicad_sym Publish 0.1.0 · Ray 5d ago
fw342-tl-e-vb.lbr Publish 0.1.0 · Ray 5d ago
fw342-tl-e-vb.step Publish 0.1.0 · Ray 5d ago
package.json Publish 0.1.0 · Ray 5d ago
page.json Set visibility: public · Ray 5d ago
README.md Publish 0.1.0 · Ray 5d ago
verification.json Verified: Published by the parts factory: tier lcsc, 8 pins · Ray 5d ago

FW342-TL-E-VB

VBsemi Elec · MOSFETs · SO-8

FW342-TL-E-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source terminal of the N-channel MOSFET, whose source-drain diode current is rated 2.6 A at TC = 25 °C.
2 G1 input Gate of the N-channel MOSFET, with gate-source voltage rated ±20 V.
3 S2 passive Source terminal of the P-channel MOSFET, whose source-drain diode current is rated -2.6 A at TC = 25 °C.
4 G2 input Gate of the P-channel MOSFET, with gate-source voltage rated ±20 V.
5 D2 passive Drain of the P-channel MOSFET, with drain-source voltage rated -30 V.
6 D2 passive Drain of the P-channel MOSFET, with drain-source voltage rated -30 V.
7 D1 passive Drain of the N-channel MOSFET, with drain-source voltage rated 30 V.
8 D1 passive Drain of the N-channel MOSFET, with drain-source voltage rated 30 V.

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Transistors/Thyristors
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Drain-Source Voltage N-channel VDS 30 V 1
Drain-Source Voltage P-channel VDS -30 V 1
Gate-Source Voltage VGS -20 20 V 1
Continuous Drain Current N-channel ID 6.8 A TA = 25 °C 1
Continuous Drain Current P-channel ID -6.6 A TA = 25 °C 1
Pulsed Drain Current N-channel IDM 40 A 10 µs pulse width 1
Pulsed Drain Current P-channel IDM -40 A 10 µs pulse width 1
Single Pulse Avalanche Current N-channel IAS 10 A L = 0.1 mH 1
Single Pulse Avalanche Current P-channel IAS 20 A L = 0.1 mH 1
Single Pulse Avalanche Energy EAS 520 mJ 1
Operating Junction and Storage Temperature Range TJ, Tstg -55 150 °C 1
Maximum Junction-to-Ambient N-channel RthJA 50 62.5 °C/W t ≤ 10 s 1
Maximum Junction-to-Ambient P-channel RthJA 47 62.5 °C/W t ≤ 10 s 1
Maximum Junction-to-Foot (Drain) N-channel RthJF 30 40 °C/W Steady state 1
Maximum Junction-to-Foot (Drain) P-channel RthJF 29 38 °C/W Steady state 1
Maximum Junction-to-Ambient N-channel steady state RthJA 120 °C/W Steady state 1
Maximum Junction-to-Ambient P-channel steady state RthJA 110 °C/W Steady state 1
Drain-Source Breakdown Voltage N-channel V(BR)DSS 30 V VGS = 0 V, ID = 250 µA 2
Drain-Source Breakdown Voltage P-channel V(BR)DSS -30 V VGS = 0 V, ID = -250 µA 2
Gate Threshold Voltage N-channel VGS(th) 1 2 V VDS = VGS, ID = 250 µA 2
Gate Threshold Voltage P-channel VGS(th) -2 -1 V VDS = VGS, ID = -250 µA 2
Gate-Body Leakage N-channel IGSS -100 100 nA VDS = 0 V, VGS = ± 12 V 2
Gate-Body Leakage P-channel IGSS -100 100 nA VDS = 0 V, VGS = ± 12 V 2
Zero Gate Voltage Drain Current N-channel IDSS 1 µA VDS = 30 V, VGS = 0 V 2
Zero Gate Voltage Drain Current P-channel IDSS -1 µA VDS = -30 V, VGS = 0 V 2
Zero Gate Voltage Drain Current N-channel TJ = 55 °C IDSS 10 µA VDS = 30 V, VGS = 0 V, TJ = 55 °C 2
Zero Gate Voltage Drain Current P-channel TJ = 55 °C IDSS -10 µA VDS = -30 V, VGS = 0 V, TJ = 55 °C 2
Drain-Source On-State Resistance N-channel RDS(on) 0.02 Ω VGS = 8 V, ID = 6.7 A 2
Drain-Source On-State Resistance N-channel RDS(on) 0.024 Ω VGS = 4.5 V, ID = 6.6 A 2
Drain-Source On-State Resistance P-channel RDS(on) 0.04 Ω VGS = -10 V, ID = -8 A 2
Drain-Source On-State Resistance P-channel RDS(on) 0.044 Ω VGS = -8 V, ID = -6.5 A 2
Drain-Source On-State Resistance P-channel RDS(on) 0.05 Ω VGS = -4.5 V, ID = -5 A 2
Total Gate Charge N-channel Qg 6 10 nC VDS = 20 V, VGS = 10 V, ID = 10 A 2
Total Gate Charge P-channel Qg 41.5 63 nC VDS = -20 V, VGS = -10 V, ID = -10 A 2
Turn-On Delay Time N-channel td(on) 4 8 ns VDD = 20 V, RL = 3.7 Ω, ID ≅ 5.4 A, VGEN = 10 V, Rg = 1 Ω 3
Turn-On Delay Time P-channel td(on) 10 16 ns VDD = -20 V, RL = 2 Ω, ID ≅ -10 A, VGEN = -10 V, Rg = 1 Ω 3
Body Diode Voltage N-channel VSD 0.81 1.2 V IS = 5.4 A 3
Body Diode Voltage P-channel VSD -1.2 -0.77 V IS = -2 A 3

CAD (KiCad official)

  • Symbol: FW342-TL-E-VB
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: fw342-tl-e-vb-etched.step / fw342-tl-e-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fw342-tl-e-vb.step / fw342-tl-e-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (14 pp, sha256 a89b54c91ac452bf, retrieved 2026-11-02, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF