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FW102-TL-E-VB

Public Made by Adom

by adom

VBsemi Elec MOSFETs, SO-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componenttransistors-thyristorsfw102-tl-e-vbfactory-2.0.0extractor-text

Verified FW102-TL-E-VB

by Ray · last 30 Oct 2026 · 1 record · files match
SymbolFootprint3D modelPins

Verification log 1 record

30 Oct 2026RayPublished by the parts factory: tier lcsc, 8 pinsfiles match
SymbolFootprint3D modelPinsfor all variants
  • ✓component-page-verify: PASS
  • ✓cad_props: Datasheet, MPN and distributor properties match page.json
  • ✓component: FW102-TL-E-VB · SO-8 · 8 pins
  • ✓copper: 8 copper pads, none touching another net
  • ✓datasheet: all 8 pin names found in the 9-page datasheet
  • •distributor (warn): no ['digikey', 'mouser'] number
  • ✓family: SOIC-8_3.9x4.9mm_P1.27mm
  • ✓files: 7 declared files present
  • ✓hero: docs/hero.png 4000x2500
  • ✓lbr: OK: /tmp/cpv-i1_5jz_p/x.lbr is a valid EAGLE .lbr with complete deviceset
  • ✓license: CC-BY-SA-4.0
  • ✓models_3d: 2 records
  • •package_fit (skip): no component.package_dims on the page: the model is unchecked against the datasheet drawing
  • ✓pads: 8 pins = 8 pads
  • ✓pose: 2 STEP(s) Z-up, seated, centred
  • ✓symbol: 8 pins agree
  • ✓visibility: public, source open
Evidencedatasheet
Verified files✓ fw102-tl-e-vb.kicad_sym✓ fw102-tl-e-vb.kicad_mod✓ fw102-tl-e-vb.step
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Symbol & Footprint

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Contents

README

markdown

FW102-TL-E-VB

VBsemi Elec · MOSFETs · SO-8

FW102-TL-E-VB from VBsemi Elec, in a SO-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 S1 passive Source of P-channel MOSFET 1 (drain-source voltage rating -30 V).
2 G1 input Gate of P-channel MOSFET 1 (gate-source voltage limit ±20 V).
3 S2 passive Source of P-channel MOSFET 2 (drain-source voltage rating -30 V).
4 G2 input Gate of P-channel MOSFET 2 (gate-source voltage limit ±20 V).
5 D2 passive Drain of P-channel MOSFET 2 (continuous drain current -7.3 A at TC = 25 °C, limited by package).
6 D2 passive Drain of P-channel MOSFET 2, tied to pin 5 (pulsed drain current -32 A).
7 D1 passive Drain of P-channel MOSFET 1 (continuous drain current -7.3 A at TC = 25 °C, limited by package).
8 D1 passive Drain of P-channel MOSFET 1, tied to pin 7 (pulsed drain current -32 A).

Key specifications

Parameter Value
Manufacturer VBsemi Elec
Package SO-8
Category Transistors/Thyristors
Pins 8

CAD (KiCad official)

  • Symbol: FW102-TL-E-VB
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SO-8 (KiCad packages3D, STEP)
  • 3D model files: fw102-tl-e-vb-etched.step / fw102-tl-e-vb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fw102-tl-e-vb.step / fw102-tl-e-vb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: VBsemi Elec datasheet (9 pp, sha256 02ef859c90cbb145, retrieved 2026-10-30, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF