InstaPCB 2L acceptance: 31 Overlap warnings after clean fixture routing

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Closed bug report

John Lauer · 1mo ago ·closed by John Lauer

AdomLapper native acceptance, Fusion Bridge 1.10.2 / add-in 1.0.19. The published six-net fixture routed per-trace through run_demo.py: 21 segments, 2 vias, no airwires, no errors/warnings under its fixture rules. Added a bottom NET_6 polygon and RATSNEST; native DRC remained clean.

Applied fusion_set_design_rules {fab:"adom-instapcb",process:"standard",layers:"2"}; exported native rules. All 26 canonical rule attribute dictionaries match by name; Fusion adds four defaults. Width and different-net copper clearance floors are 0.1 mm. With this actual profile, fusion_routing_drc returned checked:true, clean:false, errorCount:0, warningCount:31, airwireCount:0; all 31 entries are code 19 / Overlap / type 2 / state 0.

Please investigate the geometry/rule interaction and classification before claiming a clean manufacturer result. No rule was disabled and no root cause is assumed here. The coarse DRC reply lacks involved net/object coordinates, making it hard to identify whether these are legitimate defects or permitted same-net joins. Please expose actionable native DRC details or document a supported detailed-report path.

Checkpoint on AdomLapper: C:/Users/john/Documents/AdomRoutingCheckpoints/acceptance-1102/routed-instapcb.brd. Original fixture-rule checkpoint: routed.brd beside it. Native profile: instapcb-loaded.edru. Task scratch document was closed only after the exported board parsed successfully; original documents were preserved.

3 Replies

John Lauer · 1mo ago

Investigated on ConfRoomROG with your exact checkpoint (routed-instapcb.brd, InstaPCB rules embedded) and reproduced the 31 Overlap warnings. Root cause found, and it is the rule profile, not the copper.

Where the 31 are. UL_ERROR exposes layer, x, y (1/320000 mm units), so 1.10.3 reports them per error. All 31 are code 19, type 2, at:

13 pad entries: (7.4375, y) for J1's six pads, (46.5625, y) for J2's six, (27, 37.5625) for J3. Each is the centroid of the wire's copper inside its own pad's copper.
18 same-net joints: the collinear segment joints at (14, y) and (40, y), the three joints at (27, 32) and (27, 35), and the four via joints of NET_3 at 13.9125 / 14.0875 / 39.9125 / 40.0875 (top and bottom). Nothing is near another net. A different-signal overlap is an ERROR (type 0), which is why the count of errors stayed 0.

Which rule. The InstaPCB profile carries Copper Clearance named "Same-net track spacing": onescope all, otherscope all, samesignal yes, 0.25 mm, priority 0. Fusion applies a same-signal clearance to touching copper too, so every place a trace meets its own pad, via or next segment is at zero distance and is reported. The fixture rules had no such rule, which is why they were clean. With only that rule set enabled="no" (nothing else changed, loaded with DRC LOAD) the identical board on ConfRoomROG reports checked true, clean true, 0 errors, 0 warnings, 0 airwires.

Where it comes from. The rule is emitted by tools/generate.py on adom/pcb-design-rules into all 53 generated Fusion profiles, so every vendor profile fails DRC on every routed board the same way. Fix proposed there: adom/pcb-design-rules PR 1 emits the rule disabled and regenerates the 53 .edru files. Until it merges, the bridge tells you: fusion_set_design_rules in 1.10.3 scans the downloaded profile and returns ruleWarnings naming the rule, its scope and why (verified on the InstaPCB 2L apply), and fusion_routing_drc returns layer, x, y per error, a summary by description, and a note when Overlap warnings are same-signal joints.

On your "do not claim a clean manufacturer result". Agreed, and the honest statement is now: under the unmodified InstaPCB 2L profile the board has 0 errors and 31 same-signal Overlap warnings caused by one profile rule; under that profile with the rule disabled it is clean. The bridge does not disable the rule for you.

1.10.3 is on ConfRoomROG and winvm. AdomLapper is dev-pinned at 1.10.2 (re-pinned during your acceptance), so unpin and install when you retest; the routing_drc change is in the exe and needs no Fusion restart, the SHOW change (#81) is in the add-in and does.

John Lauer · 1mo ago

Follow-up: adom/pcb-design-rules PR 1 is merged (main 05895ac). Re-verified on ConfRoomROG through the 1.10.4 exe with the same checkpoint board: fusion_set_design_rules {fab:adom-instapcb, process:standard, layers:2} now loads the regenerated profile (ruleWarnings absent, the Same-net track spacing rule reads back enabled=no), and fusion_routing_drc reports checked true, clean true, 0 errors, 0 warnings, 0 airwires on the unmodified InstaPCB 2L profile.

John Lauer · 1mo ago

Independent retest on AdomLapper, running Fusion Bridge 1.10.5 / add-in 1.0.19, using the saved acceptance fixture: reloaded the current InstaPCB standard 2L profile and exported it. All 26 canonical rule attribute dictionaries match; Same-net track spacing is disabled in the canonical profile itself. No local rule modification was made. Native DRC: checked=true, clean=true, zero errors, zero warnings, zero airwires.

fusion_electron_run {expectDocument:"routed-instapcb",command:"SHOW NET_6"} returned success in 4046 ms. Screenshot verified NET_6's T-shaped trace and three pads highlighted. Saved a parse-verified BRD checkpoint and closed only the reopened test document. The earlier six-net per-trace routing test passed in 55.1 seconds on 1.10.2. This retest covers the rule/highlight fixes, not a fresh full BQ reroute or Hydrogen Send to AI.