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FU6832L

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Fortior Tech Brushless DC (BLDC) Motor Driver, LQFP-48(7x7). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FU6832L

Fortior Tech · Brushless DC (BLDC) Motor Driver · LQFP-48(7x7)

FU6832L from Fortior Tech, in a LQFP-48(7x7). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.2/C2M/A2M bidirectional GPIO with configurable external interrupt INT1 input; also serves as CMP2 negative input and AMP2 negative input.
2 P2.3/AD1/A2O/C4P/DA1 bidirectional GPIO with configurable external interrupt INT1 input; also ADC channel 1 input, AMP2 output, CMP4 positive input, and DAC1 output (no buffer).
3 P2.4/AD2 bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 2 input, which can be used for bus voltage sampling.
4 P2.5/AD3 bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 3 input.
5 P2.6/C3M/DA0/AD11 bidirectional GPIO with configurable external interrupt INT1 input; also CMP3 negative input, DAC0 output (no buffer), and ADC channel 11 input.
6 P2.7/AD4/C3P/A0O/C4M bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 4 input, which can be used for bus current sampling; also CMP3 positive input, AMP0 output, and CMP4 negative input.
7 P3.0/A0M bidirectional GPIO; also AMP0 negative input.
8 P3.1/A0P bidirectional GPIO; also AMP0 positive input.
9 P3.2/AD5/VHALF bidirectional GPIO; also ADC channel 5 input and VREF/2 reference voltage output, which can be externally decoupled with a 1μF capacitor.
10 P3.3/AD6 bidirectional GPIO; ADC channel 6 input.
11 P3.4/AD7 bidirectional GPIO; ADC channel 7 input.
12 P3.5/VREF bidirectional GPIO; ADC reference voltage external input or internal VREF output, requires an external 1μF to 4.7μF capacitor.
13 P4.4 bidirectional GPIO port P4.4 with no alternate function listed in the pin table.
14 P4.5 bidirectional GPIO port P4.5 with no alternate function listed in the pin table.
15 P3.6/HAL2/RXD2 bidirectional GPIO; Hall-IC2 logic level input; UART2 RXD input or LIN RXD input.
16 P3.7/HAL1/TXD2 bidirectional GPIO; Hall-IC1 logic level input; UART2 TXD output or LIN TXD output.
17 P0.0/TIM4S/TXD2S/SDA bidirectional GPIO with configurable external interrupt INT0 input; also Timer4 alternate input/output, UART2/LIN TXD alternate output, and I2C SDA which can be set to open-drain output.
18 P0.1/RXD2S/DBG/TIM4/TIM3S/SCL bidirectional GPIO with configurable external interrupt INT0 input; also UART2/LIN RXD alternate input, debug signal output, Timer4 input/output, Timer3 alternate input/output, and I2C SCL which can be set to open-drain output.
19 P0.2/HAL0 bidirectional GPIO with configurable external interrupt INT0 input; Hall-IC0 logic level input.
20 P0.3 bidirectional GPIO with configurable external interrupt INT0 input.
21 P0.4/NSS bidirectional GPIO with configurable external interrupt INT0 input; SPI chip select (NSS) port.
22 P0.5/TXD/SCLK bidirectional GPIO with configurable external interrupt INT0 input; UART1 TXD output; SPI clock SCLK.
23 P0.6/RXD/MOSI bidirectional GPIO with configurable external interrupt INT0 input; UART1 RXD input; SPI MOSI (master out, slave in).
24 P0.7/MISO/CXO/TIM2S/QEPA bidirectional GPIO; SPI MISO (master in, slave out); comparator output test port; Timer2 alternate input/output; QEP encoder A input.
25 P1.0/TIM2/QEPB bidirectional GPIO with configurable external interrupt INT1 input; Timer2 input/output; QEP encoder B input.
26 P1.1/TIM3 bidirectional GPIO with configurable external interrupt INT1 input; Timer3 input/output.
27 P4.2 bidirectional GPIO port P4.2 with no alternate function listed in the pin table.
28 H_PU output Pre-driver high-side U-phase output with internal 50kΩ pull-up resistor, driving the PMOS gate.
29 H_PV output Pre-driver high-side V-phase output with internal 50kΩ pull-up resistor, driving the PMOS gate.
30 H_PW output Pre-driver high-side W-phase output with internal 50kΩ pull-up resistor, driving the PMOS gate.
31 L_U output Pre-driver low-side U-phase output with internal 25kΩ pull-down resistor, driving the NMOS gate.
32 L_V output Pre-driver low-side V-phase output with internal 25kΩ pull-down resistor, driving the NMOS gate.
33 L_W output Pre-driver low-side W-phase output with internal 25kΩ pull-down resistor, driving the NMOS gate.
34 NC unconnected Not connected.
35 VCC power_in Power input with range set by VCC_MODE: 5V to 28V in single-supply high-voltage mode (VCC_MODE=0, VDD5 from internal LDO), 3V to 5.5V in single-supply low-voltage mode (VCC_MODE=1, supplied at VDD5 with VCC shorted to VDD5), or 5V to 36V in dual-supply mode (VCC_MODE=1); requires 10μF or larger filter capacitor.
36 VSS power_in Ground.
37 VDD5 power_in Power input or internal 5V LDO output depending on VCC_MODE (see VCC pin); requires an external 1μF to 4.7μF capacitor.
38 NC unconnected Not connected.
39 RSTN/FICEK input External reset input with internal pull-up resistor; also FICE clock pin.
40 VDD18 power_out 1.8V LDO output; requires an external 1μF to 4.7μF capacitor (typical 1.85V, range 1.65V to 2.0V).
41 P1.2/FICED bidirectional GPIO with configurable external interrupt INT1 input; FICE data pin.
42 P1.3/HBIAS/C1PS/AD12 bidirectional GPIO with configurable external interrupt INT1 input; Hall bias supply, internally switched to VDD5 and capable of large current output; also CMP1 alternate positive input and ADC channel 12 input.
43 P1.4/C0P/AD10/HAL0S bidirectional GPIO with configurable external interrupt INT1 input; CMP0 positive input; ADC channel 10 input; Hall-IC0 alternate logic level input.
44 P1.5/C0M/C2PS/AD13 bidirectional GPIO with configurable external interrupt INT1 input; CMP0 negative input; CMP2 alternate positive input; ADC channel 13 input.
45 P1.6/C1P/A1P/AD9/HAL1S bidirectional GPIO with configurable external interrupt INT1 input; CMP1 positive input; AMP1 positive input; ADC channel 9 input; Hall-IC1 alternate logic level input.
46 P1.7/C1M/A1M bidirectional GPIO with configurable external interrupt INT1 input; CMP1 negative input; AMP1 negative input.
47 P2.0/AD0/A1O bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 0 input; AMP1 output.
48 P2.1/C2P/A2P/AD8/HAL2S bidirectional GPIO with configurable external interrupt INT1 input; CMP2 positive input; AMP2 positive input; ADC channel 8 input; Hall-IC2 alternate logic level input.

Key specifications

Parameter Value
Manufacturer Fortior Tech
Package LQFP-48(7x7)
Category Motor Driver ICs
Pins 48

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
工作时环境温度 TA -40 85 ℃ 57
工作时环境温度 TA -40 105 ℃ 双电源模式，VCC_MODE = 1，VDD5 = 5V，VCC < 28V 57
工作时结温 TJ -40 150 ℃ 57
储存温度 -55 150 ℃ 57
VCC 相对 VSS 的电压 -0.3 36 V 57
VDD5 相对 VSS 的电压 -0.3 6.5 V 57
VCC 工作电压 VCC 5 28 V 单电源高压模式 57
VCC 工作电压 VCC 5 36 V VCC_MODE = 1，VCC ≥ VDD5 57
VDD5 工作电压 VDD5 3 5.5 V VCC 与 VDD5 连接 57
IVCC工作电流 IVCC 20 40 mA 57
IVCC待机电流 IVCC 6 12 mA 57
IVCC睡眠电流 IVCC 50 150 μA 57
输出上升时间 15 ns 50pF 负载,从 10%上升至 90%时间，TA = 25℃ 58
输出下降时间 13 ns 50pF 负载,从 90%下降至 10%时间，TA = 25℃ 58
上拉电阻 33 kΩ 注[2]: 除 P0[2:0]、P1[6:3]、P2[1]、P3[7:6]外其他 GPIO 58
上拉电阻 5.6 kΩ 注[3]: P0[2:0]、P1[6:3]、P2[1]、P3[7:6] 58
下拉电阻 10 kΩ 注[4]: P0[1]、P1[1] 58
上桥输出拉电流 150 mA 58
上桥输出灌电流 90 mA 58
下桥输出拉电流 150 mA 58
下桥输出灌电流 180 mA 58
上桥输出上升时间 25 ns 外接 1nF 电容，从 10%上升至 90%时间 58
上桥输出下降时间 90 ns 外接 1nF 电容，从 90%下降至 10%时间 58
下桥输出上升时间 115 ns 外接 1nF 电容，从 10%上升至 90%时间 58
下桥输出下降时间 60 ns 外接 1nF 电容，从 90%下降至 10%时间 58
采样时间 3 63 ADCLK ADCLK = 12MHz 59
转换时间 13 ADCLK ADCLK = 12MHz 59
INL(积分非线性) INL 2 LSB 12 位模式 59
DNL(差分非线性) DNL 1.5 LSB 12 位模式 59
OFFSET(失调误差) OFFSET 6 LSB 12 位模式 59
SNR(信噪比) SNR 70.8 dB fIN = 350kHz 59
ENOB(有效位数) ENOB 10.5 Bit fIN = 350kHz 59
SFDR(无杂散动态范围) SFDR 68.2 dB fIN = 350kHz 59
THD(总谐波失真) THD 67 dB fIN = 350kHz 59
RIN 输入电阻 RIN 800 Ω 59
CIN 输入电容 CIN 30 pF 59
VREF VREF 4.3 4.5 4.7 V VREF_CR[VREFVSEL] = 00 59
VICMR共模输入范围 VICMR 0 V 59
VOS运放的失配电压 VOS 5 10 mV TA = 25℃ 59
AOL开环增益 AOL 80 dB RL= 100kΩ 59
UGBW 单位增益带宽 UGBW 6 10 MHz CL= 40pF 59
SR 运放的摆率 SR 10 15 V/μs CL= 40pF 59
运放放大倍数 1.88 2 2.12 AMP0_GAIN = 001 60
运放放大倍数 3.76 4 4.24 AMP0_GAIN = 010 60
运放放大倍数 7.52 8 8.48 AMP0_GAIN = 011 60
运放放大倍数 15.04 16 16.96 AMP0_GAIN = 100 60
BEMF 内置电阻 5.4 6.8 8.2 kΩ 60
BEMF 内置电阻间相对精度 1 % 60
系统时钟频率 SYSCLK 23.5 24 24.5 MHz 60
低速时钟频率 29 32.8 37 kHz 60
RSTN复位低电平最小时间 25 50 μs 60
VDD5 低电压复位电压 LVR 2.8 3 3.2 V 复位电压选择 LVR = 3.0V 60
VDD5 电压 VDD5 4.7 5 5.3 V VCC = 7V ~ 28V，VCC_MODE = 0 61
VDD18 电压 VDD18 1.65 1.85 2 V 61
θJA结温相对环境温度热阻 (LQFP48) θJA 52.4 ℃/W JEDEC 标准，2S2P PCB 61
θJA结温相对环境温度热阻 (LQFP48) θJA 72.2 ℃/W JEDEC 标准，1S0P PCB 61
θJC结温相对封装表面温度热阻 (LQFP48) θJC 17 ℃/W JEDEC 标准，1S0P PCB 61

CAD (KiCad official)

  • Symbol: FU6832L
  • Footprint: Package_QFP:LQFP-48_7x7mm_P0.5mm
  • 3D model: LQFP-48(7x7) (KiCad packages3D, STEP)
  • 3D model files: fu6832l-etched.step / fu6832l-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fu6832l.step / fu6832l.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Fortior Tech datasheet (321 pp, sha256 af54b6ac680d8b4b, retrieved 2026-10-20, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF