component

FU6831Q

Public Made by Adom

by adom

Fortior Tech Motor Driver ICs, QFN-48-EP(6x6). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

componentpower management icsfu6831qfactory-2.0.0extractor-text
Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity
main
Download ZIP Propose a change
Generated by kicad-footprint-generator · KiCad file format 20260206
Name Last commit message Last updated
docs Publish 0.1.0 · Ray 9d ago
viewers fu6831q: symbol repaired (body fitted to the names) · Ray 2d ago
fu6831q-etched.glb Publish 0.1.0 · Ray 9d ago
fu6831q-etched.step fu6831q: factory component page (tier=lcsc) · Ray 9d ago
fu6831q-hero.glb fu6831q: hero GLB from the etched model (keeps the MPN mark) · Ray 9d ago
fu6831q-hero.overlay.json Publish 0.1.0 · Ray 9d ago
fu6831q.glb Publish 0.1.0 · Ray 9d ago
fu6831q.kicad_mod Publish 0.1.0 · Ray 9d ago
fu6831q.kicad_sym fu6831q: symbol repaired (body fitted to the names) · Ray 2d ago
fu6831q.lbr fu6831q: symbol repaired (body fitted to the names) · Ray 2d ago
fu6831q.step Publish 0.1.0 · Ray 9d ago
package.json Publish 0.1.0 · Ray 9d ago
page.json Set visibility: public · Ray 9d ago
README.md Publish 0.1.0 · Ray 9d ago

FU6831Q

Fortior Tech · Motor Driver ICs · QFN-48-EP(6x6)

FU6831Q from Fortior Tech, in a QFN-48-EP(6x6). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 P2.2/C2M/A2M bidirectional GPIO with configurable external interrupt INT1 input and ~4.7K pull-up; also the differential Hall2/BEMF2 negative input and the AMP2 negative input.
2 P2.3/AD1/A2O bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 1 input that samples the amplified phase current 2 signal, and the AMP2 output.
3 P2.4/AD2 bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 2 input for the bus voltage signal.
4 P2.5/AD3 bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 3 input.
5 P2.6/C3M bidirectional GPIO with configurable external interrupt INT1 input; overcurrent reference signal input, the negative input of CMP3.
6 P2.7/AD4/C3P/A0O bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 4 input for the amplified bus current signal, positive input of CMP3 for bus-current overcurrent detection, and AMP0 output.
7 P3.0/A0M bidirectional GPIO; negative input of AMP0 used to amplify the bus current signal.
8 P3.1/A0P bidirectional GPIO; positive input of AMP0 used to amplify the bus current signal.
9 P3.2/AD5/TIM0/VHALF bidirectional GPIO; over-temperature signal input, ADC channel 5 input, Advanced timer channel 4 output, and 1/2 VDD5 or 1/2 VREF reference output that requires an external 1uF capacitor.
10 P3.3/AD6/RXD2/IR_RXD2 bidirectional GPIO; ADC channel 6 input, UART2 receive (after function transfer) and infrared receive (after function transfer).
11 P3.4/AD7/TXD2/IR_TXD2 bidirectional GPIO; analog speed control input on ADC channel 7, UART2 transmit (after function transfer) and infrared transmit (after function transfer).
12 P3.5/VREF bidirectional GPIO; ADC external reference voltage input or internal VREF output, requiring an external 1uF capacitor.
13 AVSS power_in Analog ground.
14 AVDD5 power_in Analog power input, connected externally to VDD5 with a 1uF capacitor to AVSS.
15 P3.6/XIN/ECLK bidirectional GPIO; fast clock crystal input for a 24MHz crystal, or external fast clock input.
16 P3.7/XOUT bidirectional GPIO; fast clock crystal output for the 24MHz crystal.
17 P0.0/SDA bidirectional GPIO with configurable external interrupt INT0 input; I2C SDA, open-collector output with configurable ~4.7K pull-up.
18 P0.1/SCL/TIM4 bidirectional GPIO; I2C SCL clock, open-collector output with configurable ~4.7K pull-up; Timer4 input or output.
19 P0.2/LXIN bidirectional GPIO; 32768Hz crystal input.
20 P0.3/LXOUT bidirectional GPIO; 32768Hz crystal output.
21 P0.4/NSS bidirectional GPIO; SPI slave select port.
22 P0.5/MOSI/TXD/IR_TXD bidirectional GPIO; SPI MOSI (master output or slave input), UART1 transmit (before function transfer) and infrared transmit (before function transfer).
23 P0.6/MISO/RXD/IR_RXD bidirectional GPIO; SPI MISO (master input or slave output), UART1 receive (before function transfer) and infrared receive (before function transfer).
24 P0.7/SCLK/TIM5/CXO bidirectional GPIO; SPI clock, Timer5 capture input or PWM output, and comparator output test pin.
25 P1.0/TIM2 bidirectional GPIO with configurable external interrupt INT1 input; Timer2 capture input or PWM output.
26 P1.1/TIM3 bidirectional GPIO with configurable external interrupt INT1 input; Timer3 capture input or PWM output.
27 NC unconnected Not connected.
28 H_PU output 3P3N-mode predriver high-side U-phase voltage output with internal 47K pull-up.
29 H_PV output 3P3N-mode predriver high-side V-phase voltage output with internal 47K pull-up.
30 H_PW output 3P3N-mode predriver high-side W-phase voltage output with internal 47K pull-up.
31 L_U output 3P3N-mode predriver low-side U-phase voltage output with internal 47K pull-down.
32 L_V output 3P3N-mode predriver low-side V-phase voltage output with internal 47K pull-down.
33 L_W output 3P3N-mode predriver low-side W-phase voltage output with internal 47K pull-down.
34 VBB power_out 10V LDO output that requires an external 1uF to 4.7uF capacitor.
35 VCC power_in Power input whose range depends on VCC_MODE: 5V to 24V in single-supply high-voltage mode (VCC_MODE=0, VDD5 from internal LDO), or 5V to 36V on VCC in dual-supply mode (VCC_MODE=1); requires an external 10uF or larger filter capacitor.
36 VSS power_in Digital ground.
37 VDD5 power_in Medium-voltage supply input or internal 5V LDO output depending on VCC_MODE; requires an external 1uF to 4.7uF capacitor.
38 VCC_MODE input Power-mode control input that selects the supply configuration described for the VCC pin.
39 RSTN/FICEK input External reset input with internal pull-up; also the FICE debug interface clock.
40 VDD18 power_out 1.85V LDO output that requires an external 1uF to 4.7uF capacitor.
41 P1.2/FICED bidirectional GPIO with configurable external interrupt INT1 input; FICE debug interface data.
42 P1.3/HBIAS/A3O bidirectional GPIO; Hall bias supply connected internally to VDD5 through a switch, capable of high-current output; AMP3 output.
43 P1.4/C0P/A3M bidirectional GPIO with configurable external interrupt INT1 input and ~4.7K pull-up; Timer1 switch-type Hall0 input, differential Hall0/BEMF0 positive input, and AMP3 negative input.
44 P1.5/C0M/A3P bidirectional GPIO with configurable external interrupt INT1 input and ~4.7K pull-up; differential Hall0/BEMF0 negative input and AMP3 positive input.
45 P1.6/C1P/A1P bidirectional GPIO with configurable external interrupt INT1 input and ~4.7K pull-up; Timer1 switch-type Hall1 input, differential Hall1/BEMF1 positive input, and AMP1 positive input for phase current 1 voltage signal.
46 P1.7/C1M/A1M bidirectional GPIO with configurable ~4.7K pull-up; differential Hall1/BEMF1 negative input and AMP1 negative input.
47 P2.0/AD0/A1O bidirectional GPIO with configurable external interrupt INT1 input; ADC channel 0 input that samples the amplified phase current 1 signal, and AMP1 output.
48 P2.1/C2P/A2P bidirectional GPIO with configurable external interrupt INT1 input and ~4.7K pull-up; Timer1 switch-type Hall2 input, differential Hall2/BEMF2 positive input, and AMP2 positive input for phase current 2 voltage signal.
49 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer Fortior Tech
Package QFN-48-EP(6x6)
Category Power Management ICs
Pins 49

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
TJ工作时结温 TJ -40 150 ℃ 68
储存温度 -55 150 ℃ 68
VCC 相对 VSS 的电压 VCC -0.3 36 V 68
VDD5 相对 VSS 的电压 VDD5 -0.3 6.5 V 68
VCC 工作电压 (单电源高压模式) VCC 5 24 V 单电源高压模式, TA = -40℃ ~ 85℃ 70
VCC 工作电压 (双电源高压模式) VCC 5 36 V 双电源高压模式, VCC_MODE = 1, VCC ≥ VDD5 70
工作时环境温度 TA -40 85 ℃ 70
工作时环境温度 (VCC_MODE = VDD5 = 5V) TA -40 105 ℃ VCC_MODE = VDD5 = 5V, VCC ≤ 24V 70
IVCC睡眠电流 IVCC 100 250 μA 70
VBB 电压 VBB 9 10 11 V VCC = 12V ~ 30V 82
VDD5 电压 (LDO) VDD5 4.7 5 5.3 V VCC = 7V ~ 24V, VCC_MODE = 0, TA = -40℃~ 85℃ 81
VBB 启动时间 1 ms 使能至稳定值 95%输出，1μF 电容 82
采样时间 3 63 ADCLK ADCLK = 12MHz 79
VREF (VREF_CR[VREFVSEL] = 10) VREF 4.3 4.5 4.7 V VREF_CR[VREFVSEL] = 10 80
运放失配电压 VOS VOS 5 10 mV 80
运放单位增益带宽 UGBW UGBW 6 10 MHz CL = 40pF 80
运放摆率 SR SR 10 15 V/μs CL = 40pF 80
运放共模输入范围 VICMR (min) VICMR 0 V 80
比较器共模输入范围 VICMR (min) VICMR 0 V 80
BEMF 内置电阻 5.4 6.8 8.2 KΩ 81
系统时钟频率 23.5 24 24.5 MHz TA = -40℃ ~ 85℃, VCC = 5V ~ 24V, VCC_MODE = 0 81
低速时钟频率 29 32.8 37 KHz TA = -40℃ ~ 85℃, VCC = 5V ~ 24V, VCC_MODE = 0 81
RSTN 复位低电平最小宽度 25 50 μs TA = 25℃, VCC = 15V, VCC_MODE = 0 81
芯片结温相对环境温度 ƟJA (2S2P PCB) ƟJA 36 ℃/W JEDEC 标准，2S2P PCB 83
芯片结温相对环境温度 ƟJA (1S0P PCB) ƟJA 60 ℃/W JEDEC 标准，1S0P PCB 83
芯片结温相对封装表面温度 ƟJC ƟJC 10.5 ℃/W JEDEC 标准，1S0P PCB 83
IVCC工作电流 IVCC 24 mA 70
IVCC待机电流 IVCC 6 mA 70
GPIO 输出上升时间 15 ns 50pF 负载, 从 10%上升至 90%, TA = 25℃ 73
GPIO 输出下降时间 13 ns 50pF 负载, 从 90%下降至 10%, TA = 25℃ 73
上拉电阻[2] 33 KΩ Vin = 0V; 除 P0[1:0]、P1[7:4]、P2[1]外其他 GPIO 73
上拉电阻[3] 5 KΩ Vin = 0V; P0[1:0]、P1[7:4]、P2[1] 73
上桥输出拉电流 150 mA 77
上桥输出灌电流 90 mA 77
下桥输出拉电流 150 mA 77
下桥输出灌电流 180 mA 77
上桥输出上升时间 25 ns 1nF 负载, 从 10%上升至 90% 77
上桥输出下降时间 90 ns 1nF 负载, 从 90%下降至 10% 77
下桥输出上升时间 115 ns 1nF 负载, 从 10%上升至 90% 77
下桥输出下降时间 60 ns 1nF 负载, 从 90%下降至 10% 77
下桥输出高电平 10 V 77
下桥输出低电平 0 V 77
ADC INL (积分非线性) INL 2 LSB 12 位模式 79
ADC DNL (差分非线性) DNL 1.5 LSB 12 位模式 79
ADC OFFSET (失调误差) OFFSET 6 LSB 12 位模式 79
ADC 输入电阻 RIN RIN 500 Ω 79
ADC 输入电容 CIN CIN 30 pF 79
ADC 转换时间 13 ADCLK 12 位模式, ADCLK = 12MHz 79
VREF (VREF_CR[VREFVSEL] = 00) VREF 3 V VREF_CR[VREFVSEL] = 00 80
VREF (VREF_CR[VREFVSEL] = 01) VREF 4 V VREF_CR[VREFVSEL] = 01 80
VREF (VREF_CR[VREFVSEL] = 11) VREF 5 V VREF_CR[VREFVSEL] = 11, VDD5 = 5.3V, VCC_MODE = 1 80
比较器迟滞电压 VHYS (CMP_CR1[5:3] = 000) VHYS 0 mV CMP_CR1[5:3] = 000 80
比较器迟滞电压 VHYS (CMP_CR1[5:3] = 100) VHYS 10 mV CMP_CR1[5:3] = 100 80
比较器迟滞电压 VHYS (CMP_CR1[5:3] = 111) VHYS 15 mV CMP_CR1[5:3] = 111 80
比较器失配电压 VOS VOS 7 mV 80
BEMF 内置电阻间相对精度 1 % 81
VDD18 电压 VDD18 1.85 V 82

CAD (KiCad official)

  • Symbol: FU6831Q
  • Footprint: Package_DFN_QFN:QFN-48-1EP_6x6mm_P0.4mm_EP4.2x4.2mm
  • 3D model: QFN-48-EP(6x6), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
  • 3D model files: fu6831q-etched.step / fu6831q-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fu6831q.step / fu6831q.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: Fortior Tech datasheet (292 pp, sha256 d5a21e4e7fe9a48c, retrieved 2026-10-29, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF