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FU6522N

Fortior Tech · Microcontrollers (MCU/MPU/SOC) · QFN-32-EP(4x4)

FU6522N from Fortior Tech, in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	P2.1/C2P/A2P/AD8/HAL2S	bidirectional	GPIO that also serves as CMP2 positive input, AMP2 positive input, ADC channel 8 input, and Hall-IC2 logic level input after function switching.
2	P2.2/C2M/A2M	bidirectional	GPIO that also serves as CMP2 negative input and AMP2 negative input.
3	P2.3/AD1/A2O/C4P/DA1	bidirectional	GPIO, configurable as INT1 input, that also serves as ADC channel 1 input, AMP2 output, CMP4 positive input, and DAC1 output without buffer.
4	P2.4/AD2	bidirectional	GPIO that also serves as ADC channel 2 input for bus voltage sampling.
5	P2.7/AD4/C3P/A0O/C4M	bidirectional	GPIO, configurable as INT1 input, that also serves as ADC channel 4 input for bus current sampling, CMP3 positive input, AMP0 output, and CMP4 negative input.
6	P3.0/A0M	bidirectional	GPIO that also serves as AMP0 negative input.
7	P3.1/A0P	bidirectional	GPIO that also serves as AMP0 positive input.
8	P3.2/AD5/VHALF	bidirectional	GPIO that also serves as ADC channel 5 input and 1/2 VREF voltage output, which requires a 1μF external capacitor.
9	P3.4/AD7/C3PS/C4MS	bidirectional	GPIO that also serves as ADC channel 7 input, CMP3 positive input and CMP4 negative input after function switching; when AMP_CR0[CP_EN]=1 the AMP0 output (P2.7) is delivered via a 50k Ohm resistor and a 1μF external capacitor is connected for bus average current sampling.
10	P0.0/TIM4S/TXD2S/SDA	bidirectional	GPIO, configurable as INT0 input, that also serves as Timer4 input/output and UART2 TXD output after function switching, and as I2C SDA (collector open-drain output).
11	P0.1/DBG/TIM4/TIM3S/RXD2S/SCL	bidirectional	GPIO, configurable as INT0 input, that also serves as debug port, Timer4 input/output, Timer3 input/output after switching, UART2 RXD after switching, and I2C SCL (collector open-drain output).
12	P0.5/TXD/SCLK	bidirectional	GPIO, configurable as INT0 input, that also serves as UART1 TXD output and SPI SCLK.
13	P0.6/RXD/MOSI	bidirectional	GPIO, configurable as INT0 input, that also serves as UART1 RXD input (two-wire mode, or TXD output/RXD input in single-wire mode) and SPI MOSI (master output or slave input).
14	P0.7/MISO/TIM2S/QEPA	bidirectional	GPIO that also serves as SPI MISO (master input or slave output), Timer2 input/output after function switching, and QEP encoder A input.
15	P1.0/TIM2/QEPB	bidirectional	GPIO, configurable as INT1 input, that also serves as Timer2 input/output and QEP encoder B input.
16	P1.1/TIM3	bidirectional	GPIO, configurable as INT0/INT1 input, that also serves as Timer3 input/output.
17	L_DU	output	Low-side U-phase PWM output.
18	L_DV	output	Low-side V-phase PWM output.
19	L_DW	output	Low-side W-phase PWM output.
20	H_DU	output	High-side U-phase PWM output.
21	H_DV	output	High-side V-phase PWM output.
22	H_DW	output	High-side W-phase PWM output.
23	VSS	power_in	Ground.
24	VDD5	power_in	Power input with a 1μF ~ 4.7μF external capacitor.
25	P4.7/TIM3S2/RXD2S2/RSTN/FICEK	input	GPIO P4.7 input that also serves as Timer3 input and UART2 RXD input after function switching, external reset input with built-in pull-up resistor (RSTN), and FICE SCL.
26	P1.2/TIM4S2/TXD2S2/FICED	bidirectional	GPIO, configurable as INT1 input, that also serves as Timer4 input/output and UART2 TXD output after function switching, and FICE SDA.
27	P1.3/HBIAS/C1PS/A3O/AD12	bidirectional	GPIO, configurable as INT1 input, that also serves as Hall bias power supply (internally connected to VDD5 via a switch), CMP1 positive input after switching, AMP3 output, and ADC channel 12 input.
28	P1.4/C0P/A3M/AD10/HAL0S	bidirectional	GPIO, configurable as INT1 input, that also serves as CMP0 positive input, AMP3 negative input, ADC channel 10 input, and Hall0 logic level input after function switching.
29	P1.5/C0M/C2PS/A3P/AD13	bidirectional	GPIO, configurable as INT1 input, that also serves as CMP0 negative input, CMP2 positive input after switching, AMP3 positive input, and ADC channel 13 input.
30	P1.6/C1P/A1P/AD9/HAL1S	bidirectional	GPIO, configurable as INT1 input, that also serves as CMP1 positive input, AMP1 positive input, ADC channel 9 input, and Hall-IC1 logic level input after function switching.
31	P1.7/C1M/A1M	bidirectional	GPIO, configurable as INT1 input, that also serves as CMP1 negative input and AMP1 negative input.
32	P2.0/AD0/A1O	bidirectional	GPIO, configurable as INT1 input, that also serves as ADC channel 0 input and AMP1 output.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Fortior Tech
Package	QFN-32-EP(4x4)
Category	Embedded Processors & Controllers
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
Operating Junction Temperature	TJ	-40		125	℃		75
Storage Temperature	Tstg	-55		125	℃		75
VDD5 to VSS Voltage		-0.3		6.5	V		75
RSTN/GPIO to VSS Voltage		-0.3			V		75
Junction-to-ambient Temperature Thermal Resistance	θJA		47		℃/W	JEDEC standard, 2S2P PCB	91
Junction-to-ambient Temperature Thermal Resistance	θJA		74		℃/W	JEDEC standard, 1S0P PCB	91
Junction-to-case Temperature Thermal Resistance	θJC		20		℃/W	JEDEC standard, 1S0P PCB	91
Common-mode Input Voltage Range	VICMR	0			V		89
Operational Amplifier Offset Voltage	VOS		5	10	mV	TA = 25℃	89
Unity-gain Bandwidth	UGBW	6	10		MHz	CL = 40pF	89
Slew Rate	SR	10	15		V/μs	CL = 40pF	89
Operational Amplifier Gain		1.88	2	2.12	-	AMP_CR1[AMP0_GAIN] = 001	89
Operational Amplifier Gain		3.76	4	4.24	-	AMP_CR1[AMP0_GAIN] = 010	89
Operational Amplifier Gain		7.5	8	8.5	-	AMP_CR1[AMP0_GAIN] = 011	89
Operational Amplifier Gain		15	16	17	-	AMP_CR1[AMP0_GAIN] = 100	89
BEMF Built-in Resistor		5.4	6.8	8.2	kΩ		89
System Clock Rate		23.5	24	24.5	MHz		89
Low-speed Clock Rate		29	32.8	37	kHz		89
Minimum Time for RSTN Released to Low		50			μs		90
VDD5 Reset Threshold Reset Voltage		2.8	3	3.2	V	LVR = 3.0V	90
Sampling Time		3		63	ADCLK		86

CAD (KiCad official)

Symbol: FU6522N
Footprint: Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm
3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
3D model files: fu6522n-etched.step / fu6522n-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fu6522n.step / fu6522n.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Fortior Tech datasheet (340 pp, sha256 90037bb9049e4f63, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF