component
FT8161N
Public Made by Adomby adom
Fortior Tech(峰岹) Brushless DC (BLDC) Motor Driver, QFN-32-EP(4x4). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownFT8161N
Fortior Tech(峰岹) · Brushless DC (BLDC) Motor Driver · QFN-32-EP(4x4)
FT8161N from Fortior Tech(峰岹), in a QFN-32-EP(4x4). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0M | input | Negative input of AMP0 (current-sense amplifier channel 0). |
| 2 | VREF | power_in | ADC reference voltage output that needs an external 1 µF or larger capacitor to ground, used only for internal digital and analog circuits and not to supply external circuits. |
| 3 | EU/HUP | input | Phase U back-EMF divider input in sensorless mode, and positive input of the phase U differential Hall signal or switch-Hall input in sensored mode. |
| 4 | A1M/HUM | input | Negative input of AMP1, and negative input of the phase U differential Hall signal. |
| 5 | A1P/HVP | input | Positive input of AMP1, and positive input of the phase V differential Hall signal. |
| 6 | EV/HVM | input | Phase V back-EMF divider input in sensorless mode, and negative input of the phase V differential Hall signal or switch-Hall input in sensored mode. |
| 7 | EW/HWM | input | Phase W back-EMF divider input in sensorless mode, and negative input of the phase W differential Hall signal or switch-Hall input in sensored mode. |
| 8 | A2P/HWP | input | Positive input of AMP2, and positive input of the phase W differential Hall signal. |
| 9 | A2M | input | Negative input of AMP2. |
| 10 | VBUS | power_in | DC bus voltage input after resistor divider. |
| 11 | DIR | input | Motor direction control with internal pull-up (default high): high gives forward rotation with output phase sequence U-->V-->W, low gives reverse rotation with sequence U-->W-->V. |
| 12 | SPEED/SCL | bidirectional | Digital PWM speed-control input (PWM frequency range 100 Hz to 100 kHz), which becomes the I2C clock line (SCL) in I2C speed-control mode. |
| 13 | FG/RD_SDA | bidirectional | Open-drain speed-feedback (FG) or fault-indication (RD, output high in fault state) output, which becomes the open-drain I2C data line (SDA) in I2C mode. |
| 14 | VSS | power_in | Digital ground. |
| 15 | LU | output | 6N pre-driver PWM output for the U-phase low-side power switch. |
| 16 | LV | output | 6N pre-driver PWM output for the V-phase low-side power switch. |
| 17 | LW | output | 6N pre-driver PWM output for the W-phase low-side power switch. |
| 18 | VSU | power_in | 6N pre-driver U-phase input used as the ground reference for the U-phase high-side bootstrap. |
| 19 | HU | output | 6N pre-driver PWM output for the U-phase high-side power switch. |
| 20 | VBU | power_in | U-phase high-side bootstrap supply; VBU relative to VSU is specified at a maximum of 18 V. |
| 21 | VSV | power_in | 6N pre-driver V-phase input used as the ground reference for the V-phase high-side bootstrap. |
| 22 | HV | output | 6N pre-driver PWM output for the V-phase high-side power switch. |
| 23 | VBV | power_in | V-phase high-side bootstrap supply; VBV relative to VSV is specified at a maximum of 18 V. |
| 24 | VSW | power_in | 6N pre-driver W-phase input used as the ground reference for the W-phase high-side bootstrap. |
| 25 | HW | output | 6N pre-driver PWM output for the W-phase high-side power switch. |
| 26 | VBW | power_in | W-phase high-side bootstrap supply; VBW relative to VSW is specified at a maximum of 18 V. |
| 27 | VDRV | power_in | 6N pre-driver supply, 7 V to 18 V, decoupled with an external 1 µF to 10 µF capacitor. |
| 28 | VCC | power_in | Power supply input, 7 V to 18 V. |
| 29 | ASPEED | input | Analog voltage speed-control input, valid over 0 V to VDD5. |
| 30 | VDD5 | power_out | 5 V LDO output with an operating voltage range of 3 V to 5.5 V. |
| 31 | ICP | input | Overcurrent detection analog input used for current limiting in sensored SVPWM mode. |
| 32 | A0P | input | Positive input of AMP0. |
| 33 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Fortior Tech(峰岹) |
| Package | QFN-32-EP(4x4) |
| Category | Motor Driver ICs |
| Pins | 33 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| 工作时环境温度 TA | TA | -40 | 85 | ℃ | 19 | ||
| 工作时环境温度 TA | TA | -40 | 105 | ℃ | VCC ≤ 12V, Ivcc ≤30mA | 19 | |
| 工作时结温 TJ | TJ | -40 | 150 | ℃ | 19 | ||
| 储存温度 | -55 | 150 | ℃ | 19 | |||
| VCC 相对 VSS 的电压 | VCC | -0.3 | 30 | V | 19 | ||
| VDD5相对VSS的电压 | VDD5 | -0.3 | 5 | 6.5 | V | 19 | |
| VDRV 相对 VSS 的电压 | VDRV | -0.3 | 25 | V | 19 | ||
| 高压浮动绝对电压 VBU,BV,BW | VBU,BV,BW | -0.3 | 160 | V | 19 | ||
| 低侧输出电压 VLU,LV,LW | VLU,LV,LW | -1.3 | V | 19 | |||
| 其余 IO 相对 VSS 电压 | -0.3 | V | 19 | ||||
| VCC/VDRV 工作电压 | 7 | 18 | V | 19 | |||
| VDD5 工作电压 | VDD5 | 3 | 5.5 | V | 19 | ||
| VBU,BV,BW浮动电压 | VBU,BV,BW | 160 | V | 19 | |||
| VBU,BV,BW相对于 VSU,SV,SW | 18 | V | 19 | ||||
| 系统时钟频率 | 23.5 | 24 | 24.5 | MHz | 19 | ||
| IVCC工作电流 | IVCC | 15 | 25 | mA | 19 | ||
| IVCC待机电流 | IVCC | 5 | 7 | 10 | mA | 19 | |
| IVCC睡眠电流 | IVCC | 100 | μA | 19 | |||
| VCC 欠压保护跳闸电压 | 6.5 | 7 | 7.5 | V | 19 | ||
| VCC 欠压保护复位电压 | 7.5 | 8 | 8.5 | V | 19 | ||
| VOH DRV 高电平输出电压 | VOH | 0.2 | 0.34 | V | IO = 20mA | 20 | |
| VOL DRV 低电平输出电压 | VOL | 0.1 | 0.17 | V | IO = 20mA | 20 | |
| IOH DRV 高电平输出短路脉冲电流 | IOH | 0.5 | 0.8 | A | VO = 0V | 20 | |
| IOL DRV 低电平输出短路脉冲电流 | IOL | 0.5 | 0.8 | A | VO = 15V | 20 | |
| PWM 调速频率范围 | 100 | Hz | 20 | ||||
| CLOCK 调速频率范围 | 20 | 1400 | Hz | 20 | |||
| VDRV 工作电压 | VDRV | 7 | 18 | V | 20 | ||
| 高侧浮动电压 VBU,BV,BW | VBU,BV,BW | 140 | V | 20 | |||
| VDRV 欠压保护开启电压 | 4.3 | 4.8 | 5.3 | V | 20 | ||
| VDRV 欠压保护关断电压 | 4 | 4.5 | 5 | V | 20 | ||
| VDRV 欠压保护迟滞电压 | 0.2 | 0.3 | V | 20 | |||
| 输出上升时间 | 30 | 70 | ns | 1nF 负载，从 10%上升至 90%时间 | 20 | ||
| 输出下降时间 | 30 | 70 | ns | 1nF 负载，从 90%下降至 10%时间 | 20 | ||
| ASPEED 调速输入电压范围 | ASPEED | 0 | V | 21 | |||
| θJA 结温相对环境温度热阻 (JEDEC 2S2P PCB) | θJA | 47 | ℃/W | JEDEC 标准，2S2P PCB | 21 | ||
| θJA 结温相对环境温度热阻 (JEDEC 1S0P PCB) | θJA | 74 | ℃/W | JEDEC 标准，1S0P PCB | 21 | ||
| θJC 结温相对封装表面温度热阻 | θJC | 20 | ℃/W | JEDEC 标准，2S2P PCB | 21 |
CAD (KiCad official)
- Symbol:
FT8161N - Footprint:
Package_DFN_QFN:QFN-32-1EP_4x4mm_P0.4mm_EP2.9x2.9mm - 3D model: QFN-32-EP(4x4) (KiCad packages3D, STEP)
- 3D model files:
ft8161n-etched.step/ft8161n-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ft8161n.step/ft8161n.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Fortior Tech(峰岹) datasheet (28 pp, sha256
b4aab6397459772f, retrieved 2026-10-20, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).