component
FT62F135-TRB
Public Made by Adomby adom
FMD(Fremont Micro Devices) Other Processors and Microcontrollers (MCUs), TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownFT62F135-TRB
FMD(Fremont Micro Devices) · Other Processors and Microcontrollers (MCUs) · TSSOP-20
FT62F135-TRB from FMD(Fremont Micro Devices), in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | GND | power_in | Ground. |
| 2 | PC1/TK0/OSC1/ICSPDAT | bidirectional | General-purpose I/O PC1 shared with Touch key 0, crystal pin 1 (OSC1) and ISP data I/O. |
| 3 | PC0/TK1/OSC2/ICSPCLK | bidirectional | General-purpose I/O PC0 shared with Touch key 1, crystal pin 2 (OSC2) and ISP clock input. |
| 4 | PB7/TK2/[P1B1]/MCLRB | bidirectional | General-purpose I/O PB7 shared with Touch key 2, remapped P1B output and external reset input MCLRB (weak pull-up to VDD when used as reset). |
| 5 | PB6 | bidirectional | General-purpose I/O PB6 shared with Touch key 3, external LVD detection input 0 and remapped P1A complementary output. |
| 6 | PB5 | bidirectional | General-purpose I/O PB5 shared with analog input channel 7, Touch key 4, external LVD detection input 1 and remapped P1A output. |
| 7 | PB4 | bidirectional | General-purpose I/O PB4 shared with Touch key 5 and internal test pin 0. |
| 8 | PB3 | bidirectional | General-purpose I/O PB3 shared with Touch key 6 and PWMD output P1D0. |
| 9 | PB2 | bidirectional | General-purpose I/O PB2 shared with Touch key 7 and PWMC output P1C0. |
| 10 | PB1/P1A0N | bidirectional | General-purpose I/O PB1 shared with P1A0N PWM complementary output. |
| 11 | PB0/AN6/[P1C1]/CLKO | bidirectional | General-purpose I/O PB0 shared with analog input channel 6, remapped P1C output and instruction clock output CLKO. |
| 12 | PA7/AN5/P1B0/[ICSPCLK1] | bidirectional | PORTA I/O PA7 with interrupt-on-change, analog input channel 5, PWMB output P1B0 and ISP mapped pin. |
| 13 | PA6/AN4/P1A0/[ICSPCLK1] | bidirectional | PORTA I/O PA6 with interrupt-on-change, analog input channel 4, P1A0 PWM output and ISP clock mapped input. |
| 14 | PA5/VREFN | bidirectional | PORTA I/O PA5 with interrupt-on-change and ADC external negative reference input VREFN. |
| 15 | PA4/AN3/VREFP/INT/BKIN/ADC_ETR/AT0 | bidirectional | PORTA I/O PA4 with interrupt-on-change, ADC input, ADC external positive reference VREFP, external interrupt INT, PWM brake input BKIN, ADC external trigger input and test pin AT0. |
| 16 | PA3/[P1D1] | bidirectional | PORTA I/O PA3 with interrupt-on-change and remapped P1D output. |
| 17 | PA2/AN2/T0CKI/[CLKO]/TKCAP/[P1D2] | bidirectional | PORTA I/O PA2 with interrupt-on-change, analog input channel 2, Timer0 external clock T0CKI, remapped system clock output, Touch CAP pin and remapped P1D output. |
| 18 | PA1/AN1/ELVD2/[P1A2] | bidirectional | PORTA I/O PA1 with interrupt-on-change, analog input channel 1, external LVD detection input 2 and remapped P1A output. |
| 19 | PA0/AN0/ELVD3/[P1A2N] | bidirectional | PORTA I/O PA0 with interrupt-on-change, analog input channel 0, external LVD detection input 3 and remapped P1A complementary output. |
| 20 | VDD | power_in | Power supply; datasheet gives wide operating range 1.9V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | FMD(Fremont Micro Devices) |
| Package | TSSOP-20 |
| Category | Embedded Processors & Controllers |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating voltage range | VDD | 1.9 | 5.5 | V | 1 | ||
| Operating temperature | -40 | 85 | °C | 134 | |||
| Storage temperature | -40 | 125 | °C | 134 | |||
| HIRC calibration range | 15.84 | 16 | 16.16 | MHz | 25°C, VDD = 2.5V | 134 | |
| HIRC variation over temperature | 4 | % | ±4.0%, -40~85°C, VDD = 2.5V | 134 | |||
| HIRC variation over supply voltage | -1 | 1 | % | 25°C, VDD = 1.9~5.5V | 134 | ||
| HIRC operating current | IHIRC | 40 | μA | 25°C, VDD = 3.0V | 134 | ||
| HIRC startup time | 2.5 | μs | 25°C, VDD = 3.0V | 134 | |||
| LIRC oscillation frequency | 30.4 | 32 | 33.6 | kHz | 25°C, VDD = 2.5V | 134 | |
| LIRC variation over temperature | -2 | 2 | % | -40 ~ 85°C, VDD = 2.5V | 134 | ||
| LIRC variation over supply voltage | -1 | 1 | % | 25°C, VDD = 1.9~5.5V | 134 | ||
| LIRC operating current | ILIRC | 1.3 | μA | 25°C, VDD = 3.0V | 134 | ||
| LIRC startup time | 4.6 | μs | 25°C, VDD = 3.0V | 134 | |||
| LVR operating current | ILVR | 16.2 | μA | 25°C, VDD = 3.3V | 135 | ||
| LVR threshold (2.0V setting) | VLVR | 1.94 | 2 | 2.06 | V | 25°C | 135 |
| LVR threshold (2.2V setting) | VLVR | 2.13 | 2.2 | 2.27 | V | 25°C | 135 |
| LVR threshold (2.5V setting) | VLVR | 2.42 | 2.5 | 2.58 | V | 25°C | 135 |
| LVR threshold (2.8V setting) | VLVR | 2.72 | 2.8 | 2.88 | V | 25°C | 135 |
| LVR threshold (3.1V setting) | VLVR | 3.01 | 3.1 | 3.19 | V | 25°C | 135 |
| LVR threshold (3.6V setting) | VLVR | 3.49 | 3.6 | 3.71 | V | 25°C | 135 |
| LVR threshold (4.1V setting) | VLVR | 3.98 | 4.1 | 4.22 | V | 25°C | 135 |
| LVR delay | 125 | 157 | μs | 25°C, VDD = 1.9~5.5V | 135 | ||
| LVD operating current | ILVD | 21.4 | μA | 25°C, VDD = 3.3V | 135 | ||
| LVD threshold (1.2V setting) | VLVD | 1.16 | 1.2 | 1.24 | V | 25°C | 135 |
| LVD threshold (2.0V setting) | VLVD | 1.94 | 2 | 2.06 | V | 25°C | 135 |
| LVD threshold (2.4V setting) | VLVD | 2.33 | 2.4 | 2.47 | V | 25°C | 135 |
| LVD threshold (2.7V setting) | VLVD | 2.62 | 2.7 | 2.78 | V | 25°C | 135 |
| LVD threshold (3.0V setting) | VLVD | 2.91 | 3 | 3.09 | V | 25°C | 135 |
| LVD threshold (3.3V setting) | VLVD | 3.2 | 3.3 | 3.4 | V | 25°C | 135 |
| LVD threshold (3.6V setting) | VLVD | 3.49 | 3.6 | 3.71 | V | 25°C | 135 |
| LVD threshold (4.0V setting) | VLVD | 3.88 | 4 | 4.12 | V | 25°C | 135 |
| LVD delay | 125 | 157 | μs | 25°C, VDD = 1.9~5.5V | 135 | ||
| POR operating current | IPOR | 140 | nA | 25°C , VDD = 3.3V | 135 | ||
| POR voltage | VPOR | 1.65 | V | 25°C | 135 |
CAD (KiCad official)
- Symbol:
FT62F135-TRB - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
ft62f135-trb-etched.step/ft62f135-trb-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ft62f135-trb.step/ft62f135-trb.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: FMD(Fremont Micro Devices) datasheet (153 pp, sha256
a04bd40fbc2ff2b4, retrieved 2026-10-22, tier: lcsc) - Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).