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FT62F132-RB

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FMD Fremont Micro Devices Microcontrollers (MCU/MPU/SOC), SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FT62F132-RB

FMD Fremont Micro Devices · Microcontrollers (MCU/MPU/SOC) · SOP-14

FT62F132-RB from FMD Fremont Micro Devices, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in Ground reference pin for the device.
2 PC1/TK0/OSC1/ICSPDAT bidirectional Multiplexed GPIO PC1 with touch key TK0, crystal oscillator pin OSC1 (LP/XT modes), and ISP data I/O; source current is selectable via PSRCC and sink current via PSINKC.
3 PC0/TK1/OSC2/ICSPCLK bidirectional Multiplexed GPIO PC0 with touch key TK1, crystal oscillator pin OSC2 (LP/XT modes), and ISP clock input; source current is selectable via PSRCC and sink current via PSINKC.
4 PB7/TK2/[P1B1]/MCLRB bidirectional GPIO PB7 with touch key TK2 and P1B1 remapped PWM output; when configured as MCLRB it is the external reset input with a weak pull-up to VDD.
5 PB3/TK6/P1D0 bidirectional GPIO PB3 with touch key TK6 and P1D0 PWM output; source current is selectable via PSRCB1 and sink current via PSINKB.
6 PB2/TK7/P1C0 bidirectional GPIO PB2 with touch key TK7 and P1C0 PWM output; source current is selectable via PSRCB1 (3/6/24 mA at 5 V) and sink current via PSINKB (35/55 mA at 5 V).
7 PA7/AN5/P1B0 bidirectional GPIO PA7 with ADC analog input AN5 and P1B0 PWM output; it supports PORTA pin-change interrupt (IOCA7) and wake-up from SLEEP.
8 PB0/AN6/[P1C1]/CLKO bidirectional GPIO PB0 with ADC analog input AN6, P1C1 remapped PWM output, and CLKO instruction clock output.
9 PA6/AN4/P1A0 bidirectional GPIO PA6 with ADC analog input AN4 and P1A0 PWM output; it supports PORTA pin-change interrupt (IOCA6).
10 PA4/AN3/VREFP/INT/BKIN/ADC_ETR/AT0 bidirectional GPIO PA4 with ADC analog input AN3, external ADC positive reference VREFP, external interrupt INT, PWM brake input BKIN, ADC external trigger ADC_ETR, and test pin AT0.
11 PA2/AN2/T0CKI/[CLKO]/TKCAP/[P1D2] bidirectional GPIO PA2 with ADC analog input AN2, Timer0 external clock input T0CKI, touch module CAP pin TKCAP, system clock remap output CLKO, and P1D2 remapped PWM output.
12 PA1/AN1/ELVD2/[P1A2] bidirectional GPIO PA1 with ADC analog input AN1, external LVD detection input ELVD2, and P1A2 remapped PWM output.
13 PA0/AN0/ELVD3/[P1A2N] bidirectional GPIO PA0 with ADC analog input AN0, external LVD detection input ELVD3, and P1A2N remapped complementary PWM output.
14 VDD power_in Supply pin; the datasheet specifies a wide operating voltage range of 1.9 V to 5.5 V.

Key specifications

Parameter Value
Manufacturer FMD Fremont Micro Devices
Package SOP-14
Category Embedded Processors & Controllers
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
HIRC calibration range (16 MHz internal high-speed oscillator) 15.84 16 16.16 MHz 25°C, VDD = 2.5V 134
HIRC variation over temperature -4 4 % -40~85°C, VDD = 2.5V 134
HIRC variation over supply voltage -1 1 % 25°C, VDD = 1.9~5.5V 134
LIRC oscillation frequency (32 kHz mode) 30.4 32 33.6 kHz 25°C, VDD = 2.5V 134
LIRC variation over temperature -2 2 % -40 ~ 85°C, VDD = 2.5V 134
LIRC variation over supply voltage -1 1 % 25°C, VDD = 1.9~5.5V 134
LVR threshold (2.0 V level) VLVR 1.94 2 2.06 V 25°C 135
LVR threshold (2.2 V level) VLVR 2.13 2.2 2.27 V 25°C 135
LVR threshold (2.5 V level) VLVR 2.42 2.5 2.58 V 25°C 135
LVR threshold (2.8 V level) VLVR 2.72 2.8 2.88 V 25°C 135
LVR threshold (3.1 V level) VLVR 3.01 3.1 3.19 V 25°C 135
LVR threshold (3.6 V level) VLVR 3.49 3.6 3.71 V 25°C 135
LVR threshold (4.1 V level) VLVR 3.98 4.1 4.22 V 25°C 135
LVR delay 125 157 μs 25°C, VDD = 1.9~5.5V 135
LVD threshold (1.2 V level) VLVD 1.16 1.2 1.24 V 25°C 135
LVD threshold (2.0 V level) VLVD 1.94 2 2.06 V 25°C 135
LVD threshold (2.4 V level) VLVD 2.33 2.4 2.47 V 25°C 135
LVD threshold (2.7 V level) VLVD 2.62 2.7 2.78 V 25°C 135
LVD threshold (3.0 V level) VLVD 2.91 3 3.09 V 25°C 135
LVD threshold (3.3 V level) VLVD 3.2 3.3 3.4 V 25°C 135
LVD threshold (3.6 V level) VLVD 3.49 3.6 3.71 V 25°C 135
LVD threshold (4.0 V level) VLVD 3.88 4 4.12 V 25°C 135
LVD delay 125 157 μs 25°C, VDD = 1.9~5.5V 135
Operating temperature -40 85 °C 134
Storage temperature -40 125 °C 134

CAD (KiCad official)

  • Symbol: FT62F132-RB
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: ft62f132-rb-etched.step / ft62f132-rb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft62f132-rb.step / ft62f132-rb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FMD Fremont Micro Devices datasheet (153 pp, sha256 a04bd40fbc2ff2b4, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF