# FT61F02F-MRB

**FMD Fremont Micro Devices** · Microcontrollers (MCU/MPU/SOC) · MSOP-10

FT61F02F-MRB from FMD Fremont Micro Devices, in a MSOP-10. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VDD | power_in | Supply pin; the datasheet gives the operating supply as VDD (VPOR ≤ 2.0 V) VPOR to 5.5 V, with the 5 V, 25 °C conditions used for the stated ratings. |
| 2 | PA7 | bidirectional | Digital I/O (PORTA bit 7, PORTA change interrupt, 30 mA source / 23 mA sink at 5 V, 25 °C) that also serves as Timer1 clock input T1CKI and, when FOSC is configured, the OSC1/CLKI oscillator or external clock input. |
| 3 | PA6 | bidirectional | Digital I/O (PORTA bit 6, PORTA change interrupt, 30 mA source / 23 mA sink at 5 V, 25 °C) that also serves as OSC2/crystal output, CLKO instruction-clock output and Timer1 gate input T1G, depending on the FOSC configuration. |
| 4 | PC3 | bidirectional | Digital I/O (PORTC bit 3) with weak pull-down support, 30 mA source / 23 mA sink at 5 V, 25 °C, that can also be configured as PWM4 or ECCP output P1C. |
| 5 | PC2 | bidirectional | Digital I/O (PORTC bit 2) with weak pull-down support, 30 mA source / 23 mA sink at 5 V, 25 °C, that can also be configured as ADC analog input AN6, PWM5 or ECCP output P1D. |
| 6 | PC4 | bidirectional | Digital I/O (PORTC bit 4), 30 mA source / 23 mA sink at 5 V, 25 °C, that can also be configured as comparator 2 output C2OUT, PWM3 or ECCP output P1B. |
| 7 | PA2 | bidirectional | Digital I/O (PORTA bit 2, PORTA change interrupt), 30 mA source / 23 mA sink at 5 V, 25 °C, that can also be configured as ADC analog input AN2, comparator 1 output C1OUT or Timer0 clock input T0CKI. |
| 8 | PA1 | bidirectional | Digital I/O (PORTA bit 1, PORTA change interrupt), 30 mA source / 23 mA sink at 5 V, 25 °C, that is also the ISP data pin ISPDAT and can be configured as ADC analog input AN1 or comparator 1 inverting input C1IN-. |
| 9 | PA0 | bidirectional | Digital I/O (PORTA bit 0, PORTA change interrupt), 30 mA source / 23 mA sink at 5 V, 25 °C, that is also the ISP clock pin ISPCLK and can be configured as ADC analog input AN0 or comparator 1 non-inverting input C1IN+. |
| 10 | GND | power_in | Ground reference pin for the device. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | FMD Fremont Micro Devices |
| Package | MSOP-10 |
| Category | Embedded Processors & Controllers |
| Pins | 10 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Operating ambient temperature, grade 3 |  | -40 |  | 85 | °C |  | 96 |
| Operating ambient temperature, grade 2 |  | -40 |  | 105 | °C |  | 96 |
| Operating ambient temperature, grade 1 |  | -40 |  | 125 | °C |  | 96 |
| Storage temperature |  | -40 |  | 125 | °C |  | 96 |
| Power supply voltage (printed VSS-0.3V, VSS+6.0V) |  |  |  | 6 | V | Referenced to VSS; printed minimum is VSS-0.3V | 96 |
| Fsys (SysClk) | Fsys (SysClk) |  |  | 8 | MHz | -40, 85°C, VDD = 2.0, 5.5V | 97 |
| Fsys (SysClk) | Fsys (SysClk) |  |  | 16 | MHz | -40, 85°C, VDD = 2.7, 5.5V | 97 |
| External reset pulse width | TMCLRB | 2000 |  |  | ns | 25°C | 97 |
| T0CKI high or low pulse width |  | 10 |  |  | ns | 有预分频 | 97 |
| VLVR, LVR threshold (typ 2.0 V level) | VLVR | 1.9 | 2 | 2.1 | V | 25°C | 98 |
| VLVR, LVR threshold (typ 2.2 V level) | VLVR | 2.09 | 2.2 | 2.31 | V | 25°C | 98 |
| VLVR, LVR threshold (typ 2.5 V level) | VLVR | 2.38 | 2.5 | 2.63 | V | 25°C | 98 |
| VLVR, LVR threshold (typ 2.8 V level) | VLVR | 2.66 | 2.8 | 2.94 | V | 25°C | 98 |
| VLVR, LVR threshold (typ 3.1 V level) | VLVR | 2.95 | 3.1 | 3.26 | V | 25°C | 98 |
| VLVR, LVR threshold (typ 3.6 V level) | VLVR | 3.42 | 3.6 | 3.78 | V | 25°C | 98 |
| VLVR, LVR threshold (typ 4.1 V level) | VLVR | 3.9 | 4.1 | 4.31 | V | 25°C | 98 |
| LVR delay |  |  | 125 | 157 | μs | 25°C, VDD = 2.0, 5.5V | 98 |
| VLVD, LVD threshold (typ 2.0 V level) | VLVD | 1.9 | 2 | 2.1 | V | 25°C | 98 |
| VLVD, LVD threshold (typ 2.4 V level) | VLVD | 2.28 | 2.4 | 2.52 | V | 25°C | 98 |
| VLVD, LVD threshold (typ 2.8 V level) | VLVD | 2.66 | 2.8 | 2.94 | V | 25°C | 98 |
| VLVD, LVD threshold (typ 3.0 V level) | VLVD | 2.85 | 3 | 3.15 | V | 25°C | 98 |
| VLVD, LVD threshold (typ 3.6 V level) | VLVD | 3.42 | 3.6 | 3.78 | V | 25°C | 98 |
| VLVD, LVD threshold (typ 4.0 V level) | VLVD | 3.8 | 4 | 4.2 | V | 25°C | 98 |
| LVD delay |  |  | 125 | 157 | μs | 25°C, VDD = 2.0, 5.5V | 98 |

## CAD (KiCad official)

- Symbol: `FT61F02F-MRB`
- Footprint: `Package_SO:MSOP-10_3x3mm_P0.5mm`
- 3D model: MSOP-10 (KiCad packages3D, STEP)
- 3D model files: `ft61f02f-mrb-etched.step` / `ft61f02f-mrb-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ft61f02f-mrb.step` / `ft61f02f-mrb.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [FMD Fremont Micro Devices datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8589040406982512640) (115 pp, sha256 `c673e26d7cd0b941`, retrieved 2026-10-19, tier: lcsc)
- **Datasheet language:** Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ft61f02f-mrb-datasheet.pdf)