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FT60F122A-RB

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FMD Fremont Micro Devices Microcontrollers (MCU/MPU/SOC), SOP-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FT60F122A-RB

FMD Fremont Micro Devices · Microcontrollers (MCU/MPU/SOC) · SOP-14

FT60F122A-RB from FMD Fremont Micro Devices, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 PA1/ICSPDAT bidirectional PORTA bit 1 general-purpose I/O with interrupt-on-change, also used as the ICSP/in-circuit debug data pin.
2 PA2/T0CKI/INT/[P1C]/BK0 bidirectional PORTA bit 2 I/O with interrupt-on-change; alternately serves as Timer0 external clock input T0CKI, external interrupt INT, the remapped PWM1C output P1C, and the PWM brake input BK0.
3 PC2/[P1A1N] bidirectional PORTC bit 2 I/O, which can be remapped to the PWM1A3 complementary output [P1A1N].
4 GND power_in Negative power supply (ground) input.
5 PA3/P1C bidirectional PORTA bit 3 I/O with interrupt-on-change; default output for the PWM1C channel P1C.
6 PC3/[P1A1] bidirectional PORTC bit 3 I/O, which can be remapped to the PWM1A2 output [P1A1].
7 PC4/P1A0N bidirectional PORTC bit 4 I/O; default function is the PWM1A0N complementary PWM output with dead-band control.
8 PC5/P1A0 bidirectional PORTC bit 5 I/O; default function is the PWM1A0 positive PWM output with dead-band control.
9 PA3 bidirectional PORTA bit 4 I/O with interrupt-on-change; default output for PWM1B, which can be remapped to PA5.
10 PC2 bidirectional PORTA bit 5 I/O with interrupt-on-change; when configured as MCLRB it is the external reset input with weak pull-up, and when used as ELVD it monitors an external voltage that must not exceed VDD.
11 VDD power_in Positive power supply input; operating range is 1.9 V to 5.5 V with FSYS up to 8 MHz and 2.7 V to 5.5 V at FSYS = 16 MHz.
12 PA1 bidirectional PORTA bit 7 I/O with interrupt-on-change; serves as crystal oscillator pin OSC1 or external clock input CLKI depending on the FOSC configuration.
13 PA0 bidirectional PORTA bit 6 I/O with interrupt-on-change; serves as crystal oscillator pin OSC2 or instruction clock output CLKO depending on the FOSC configuration (CLKO moves to PC5 on E-version chips).
14 PA0/ICSPCLK bidirectional PORTA bit 0 I/O with interrupt-on-change; also used as the ICSP/in-circuit debug clock pin.

Key specifications

Parameter Value
Manufacturer FMD Fremont Micro Devices
Package SOP-14
Category Embedded Processors & Controllers
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
HIRC calibration frequency range 15.76 16 16.24 MHz 25°C, VDD = 2.5V 88
HIRC variation over temperature -4 4 % -40~85°C, VDD = 2.5V 88
HIRC variation over supply voltage -1 1.5 % 25°C, VDD = 1.9~5.5V 88
LIRC oscillation frequency 30.4 32 33.6 kHz 25°C, VDD = 2.5V 88
LIRC variation over temperature -2 2 % -40 ~ 85°C, VDD = 2.5V 88
LIRC variation over supply voltage -3.5 1 % 25°C, VDD = 1.9~5.5V 88
LVR threshold (2.0 V level) VLVR 1.94 2 2.06 V 25°C 89
LVR threshold (2.2 V level) VLVR 2.13 2.2 2.27 V 25°C 89
LVR threshold (2.5 V level) VLVR 2.42 2.5 2.58 V 25°C 89
LVR threshold (2.8 V level) VLVR 2.72 2.8 2.88 V 25°C 89
LVR threshold (3.1 V level) VLVR 3.01 3.1 3.19 V 25°C 89
LVR threshold (3.6 V level) VLVR 3.49 3.6 3.71 V 25°C 89
LVR threshold (4.1 V level) VLVR 3.98 4.1 4.22 V 25°C 89
LVR delay 125 157 μs 25°C, VDD = 1.9~5.5V 89
LVD threshold (2.0 V level) VLVD 1.94 2 2.06 V 25°C 89
LVD threshold (2.4 V level) VLVD 2.33 2.4 2.47 V 25°C 89
LVD threshold (2.8 V level) VLVD 2.72 2.8 2.88 V 25°C 89
LVD threshold (3.0 V level) VLVD 2.91 3 3.09 V 25°C 89
LVD threshold (3.6 V level) VLVD 3.49 3.6 3.71 V 25°C 89
LVD threshold (4.0 V level) VLVD 3.88 4 4.12 V 25°C 89
LVD delay 125 157 μs 25°C, VDD = 1.9~5.5V 89
Operating temperature (absolute maximum) -40 85 °C 88
Storage temperature (absolute maximum) -40 125 °C 88
Supply voltage (absolute maximum) -0.3 6 V VSS-0.3V ~ VSS+6.0V, referenced to VSS 88
Port input voltage (absolute maximum) -0.3 V VSS-0.3V ~ VDD+0.3V, referenced to VSS and VDD 88
Supply voltage (recommended operating) VDD 1.9 5.5 V FSYS = 8MHz 1
Supply voltage at 16 MHz system clock (recommended operating) VDD 2.7 5.5 V FSYS = 16MHz 1
Maximum clock operating frequency FSYS 16 MHz 1
Operating temperature (industrial range) -40 85 °C 1

CAD (KiCad official)

  • Symbol: FT60F122A-RB
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOP-14 (KiCad packages3D, STEP)
  • 3D model files: ft60f122a-rb-etched.step / ft60f122a-rb-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft60f122a-rb.step / ft60f122a-rb.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FMD Fremont Micro Devices datasheet (105 pp, sha256 9f8acb80b8551ef5, retrieved 2026-10-19, tier: lcsc)
  • Datasheet language: Chinese. Pin names, descriptions, and specs on this page were extracted and translated to English by ds2sf; the linked PDF is the manufacturer original.
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF