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FT4232HQ-REEL

Public Made by Adom

by adom

FTDI USB ICs, QFN-64-EP(9x9). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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Contents

README

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FT4232HQ-REEL

FTDI · USB ICs · QFN-64-EP(9x9)

FT4232HQ-REEL from FTDI, in a QFN-64-EP(9x9). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 GND power_in 0V ground input.
2 OSCI input Oscillator input; a 12 MHz crystal is connected between OSCI and OSCO.
3 OSCO output Oscillator output; a 12 MHz crystal is connected between OSCI and OSCO.
4 VPHY power_in +3.3V internal USB PHY supply input; cannot be connected directly to the USB supply, needs a +3.3V regulator and an LC filter is recommended.
5 GND power_in 0V ground input.
6 REF input Current reference; connect via a 12K Ohm 1% resistor to GND.
7 DM bidirectional USB Data Signal Minus.
8 DP bidirectional USB Data Signal Plus.
9 VPLL power_in +3.3V internal PHY PLL supply input; an LC filter is recommended.
10 AGND power_in 0V analog ground.
11 GND power_in 0V ground input.
12 VCORE power_in +1.8V core supply voltage input.
13 TEST input IC test pin; connect to GND for normal operation.
14 RESET# input Active-low reset input; tie to VCCIO (+3.3V) if not used.
15 GND power_in 0V ground input.
16 ADBUS0 bidirectional Channel A bit 0: TXD in async serial, D0 in bit-bang, TCK/SK in MPSSE.
17 ADBUS1 bidirectional Channel A bit 1: RXD in async serial, D1 in bit-bang, TDI/DO in MPSSE.
18 ADBUS2 bidirectional Channel A bit 2: RTS# in async serial, D2 in bit-bang, TDO/DI in MPSSE.
19 ADBUS3 bidirectional Channel A bit 3: CTS# in async serial, D3 in bit-bang, TMS/CS in MPSSE.
20 VCCIO power_in +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
21 ADBUS4 bidirectional Channel A bit 4: DTR# in async serial, D4 in bit-bang, GPIOL0 in MPSSE.
22 ADBUS5 bidirectional Channel A bit 5: DSR# in async serial, D5 in bit-bang, GPIOL1 in MPSSE.
23 ADBUS6 bidirectional Channel A bit 6: DCD# in async serial, D6 in bit-bang, GPIOL2 in MPSSE.
24 ADBUS7 bidirectional Channel A bit 7: RI#/TXDEN in async serial (selectable in EEPROM, default RI#), D7 in bit-bang, GPIOL3 in MPSSE.
25 GND power_in 0V ground input.
26 BDBUS0 bidirectional Channel B bit 0: TXD in async serial, D0 in bit-bang, TCK/SK in MPSSE.
27 BDBUS1 bidirectional Channel B bit 1: RXD in async serial, D1 in bit-bang, TDI/DO in MPSSE.
28 BDBUS2 bidirectional Channel B bit 2: RTS# in async serial, D2 in bit-bang, TDO/DI in MPSSE.
29 BDBUS3 bidirectional Channel B bit 3: CTS# in async serial, D3 in bit-bang, TMS/CS in MPSSE.
30 BDBUS4 bidirectional Channel B bit 4: DTR# in async serial, D4 in bit-bang, GPIOL0 in MPSSE.
31 VCCIO power_in +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
32 BDBUS5 bidirectional Channel B bit 5: DSR# in async serial, D5 in bit-bang, GPIOL1 in MPSSE.
33 BDBUS6 bidirectional Channel B bit 6: DCD# in async serial, D6 in bit-bang, GPIOL2 in MPSSE.
34 BDBUS7 bidirectional Channel B bit 7: RI#/TXDEN in async serial (selectable in EEPROM, default RI#), D7 in bit-bang, GPIOL3 in MPSSE.
35 GND power_in 0V ground input.
36 SUSPEND# output Active low when USB is in suspend mode.
37 VCORE power_in +1.8V core supply voltage input.
38 CDBUS0 bidirectional Channel C bit 0: TXD in async serial, D0 in bit-bang.
39 CDBUS1 bidirectional Channel C bit 1: RXD in async serial, D1 in bit-bang.
40 CDBUS2 bidirectional Channel C bit 2: RTS# in async serial, D2 in bit-bang.
41 CDBUS3 bidirectional Channel C bit 3: CTS# in async serial, D3 in bit-bang.
42 VCCIO power_in +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
43 CDBUS4 bidirectional Channel C bit 4: DTR# in async serial, D4 in bit-bang.
44 CDBUS5 bidirectional Channel C bit 5: DSR# in async serial, D5 in bit-bang.
45 CDBUS6 bidirectional Channel C bit 6: DCD# in async serial, D6 in bit-bang.
46 CDBUS7 bidirectional Channel C bit 7: RI#/TXDEN in async serial (selectable in EEPROM, default RI#), D7 in bit-bang.
47 GND power_in 0V ground input.
48 DDBUS0 bidirectional Channel D bit 0: TXD in async serial, D0 in bit-bang.
49 VREGOUT power_out +1.8V integrated regulator output; connect to VCORE with a 3.3uF filter capacitor.
50 VREGIN power_in +3.3V input to the integrated 1.8V voltage regulator.
51 GND power_in 0V ground input.
52 DDBUS1 bidirectional Channel D bit 1: RXD in async serial, D1 in bit-bang.
53 DDBUS2 bidirectional Channel D bit 2: RTS# in async serial, D2 in bit-bang.
54 DDBUS3 bidirectional Channel D bit 3: CTS# in async serial, D3 in bit-bang.
55 DDBUS4 bidirectional Channel D bit 4: DTR# in async serial, D4 in bit-bang.
56 VCCIO power_in +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
57 DDBUS5 bidirectional Channel D bit 5: DSR# in async serial, D5 in bit-bang.
58 DDBUS6 bidirectional Channel D bit 6: DCD# in async serial, D6 in bit-bang.
59 DDBUS7 bidirectional Channel D bit 7: RI#/TXDEN in async serial (selectable in EEPROM, default RI#), D7 in bit-bang.
60 PWREN# output Active-low power-enable output: 0 = normal operation, 1 = USB suspend or device not configured.
61 EEDATA bidirectional EEPROM data I/O; connect directly to EEPROM Data-In and to Data-Out via a 2.2K resistor, with Data-Out pulled to VCC via 10K; tri-state during reset.
62 EECLK output Clock signal to the EEPROM; tri-state during device reset.
63 EECS bidirectional EEPROM chip select; tri-state during device reset.
64 VCORE power_in +1.8V core supply voltage input.
65 EP passive Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter Value
Manufacturer FTDI
Package QFN-64-EP(9x9)
Category Interface ICs
Pins 65

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
VCORE Operating Supply Voltage VCORE 1.62 1.8 1.98 V Ambient -40°C to +85°C 25
VCCIO Operating Supply Voltage VCCIO 2.97 3.3 3.63 V Cells are 5V tolerant 25
VREGIN Voltage regulator Input VREGIN 3 3.3 3.6 V 25
VREGOUT Voltage regulator Output VREGOUT 1.71 1.8 1.89 V 25
Regulator Current Ireg 150 mA VREGIN +3.3V 25
Core Operating Supply Current Icc1 70 mA VCORE = +1.8V Normal Operation 25
Core Reset Supply Current Icc1r 5 mA VCORE = +1.8V Device in reset state 25
Core Suspend Supply Current Icc1s 500 µA VCORE = +1.8V USB Suspend 25
PHY Operating Supply Voltage VPHY, VPLL 3 3.3 3.6 V 3.3V I/O 26
PHY Operating Supply Current Iccphy 30 60 mA High-speed operation at 480 MHz 26
PHY Operating Supply Current (suspend) Iccphy(susp) 10 50 µA USB Suspend 26
Output Voltage High Voh 2.4 3.14 V Ioh = +/-2mA, I/O Drive strength = 4mA 26
Output Voltage Low Vol 0.18 0.4 V Iol = +/-2mA, I/O Drive strength = 4mA 26
Input low Switching Threshold Vil 0.8 V LVTTL 26
Input High Switching Threshold Vih 2 V LVTTL 26
Schmitt trigger negative going threshold voltage Vt- 0.8 1.1 V 26
Schmitt trigger positive going threshold voltage Vt+ 1.6 2 V 26
Input pull-up resistance Rpu 40 75 190 kΩ Vin = 0 26
Input pull-down resistance Rpd 40 75 190 kΩ Vin =VCCIO 26
Input Leakage Current Iin 15 45 85 µA Vin = 0 26
Tri-state output leakage current Ioz -10 10 µA Vin = 5.5V or 0 26
PHY I/O Output Voltage Low Vol 0.2 V 27
PHY I/O Input low Switching Threshold Vil 0.8 V 27
PHY I/O Input High Switching Threshold Vih 2 V 27
OSCI Input Voltage Vin 2.97 3.3 3.63 V 32
OSCI Input Frequency FIn 12 MHz +/- 30ppm 32
OSCI Cycle to cycle jitter Ji 150 pS < 150 pS 32
Storage Temperature -65 150 °C 25
Ambient Operating Temperature (Power Applied) -40 85 °C 25
VCORE Supply Voltage VCORE -0.3 2 V 25
VCCIO IO Voltage VCCIO -0.3 4 V 25
DC Input Voltage, USBDP and USBDM -0.5 3.63 V 25
DC Input Voltage, High Impedance Bi-directional -0.3 5.8 V powered from VCCIO 25
DC Input Voltage, All Other Inputs -0.5 V max is VCCIO + 0.5 V 25
DC Output Current, Outputs 16 mA 25
Junction Temperature TJ -40 25 125 °C FT4232HL/FT4232HQ 27
Thermal resistance junction to ambient ѲJA 29.67 °C/W FT4232HQ 27
Thermal resistance junction to case ѲJC 14.12 °C/W FT4232HQ 27
ESD Human Body Model HBM 2 kV JEDEC EIA/JESD22-A114-B, Class 2, ±2kV 27
ESD Machine Mode MM 200 V JEDEC EIA/JESD22-A115-A, Class B, ±200V 27
ESD Charge Device Model CDM 500 V JEDEC EIA/JESD22-C101-D, Class-III, ±500V 27
Latch-up 200 mA JESD78, Trigger Class-II, ±200mA 27

CAD (KiCad official)

  • Symbol: FT4232HQ-REEL
  • Footprint: Package_DFN_QFN:QFN-64-1EP_9x9mm_P0.5mm_EP6x6mm
  • 3D model: QFN-64-EP(9x9) (KiCad packages3D, STEP)
  • 3D model files: ft4232hq-reel-etched.step / ft4232hq-reel-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft4232hq-reel.step / ft4232hq-reel.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FTDI datasheet (45 pp, sha256 19462d37a9d1e484, retrieved 2026-10-23, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF