component
FT4232H-56Q-TRAY
Public Made by Adomby adom
FTDI USB ICs, QFN-56-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
Open in new tab ↗
Loads when you scroll to it. Unloads after 5 minutes in the background.
Symbol & Footprint
Schematic Symbol
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
PCB Footprint
Open full view ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
Datasheet
Open in new tab ↗Loads when you scroll to it. Unloads after 5 minutes in the background.
README
markdownFT4232H-56Q-TRAY
FTDI · USB ICs · QFN-56-EP(8x8)
FT4232H-56Q-TRAY from FTDI, in a QFN-56-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EECS | bidirectional | EEPROM chip select; tri-state during device reset. |
| 2 | VCORE | power_in | +1.8V core supply voltage input. |
| 3 | OSCI | input | Oscillator input; a 12 MHz crystal connects to OSCI and OSCO. |
| 4 | OSCO | output | Oscillator output. |
| 5 | VPHY | power_in | +3.3V input for the internal USB PHY; must come from a +3.3V regulator (not directly from USB supply) and LC filtering is recommended. |
| 6 | REF | input | Current reference; connect via a 12K Ohm 1% resistor to GND. |
| 7 | DM | bidirectional | USB Data Signal Minus. |
| 8 | DP | bidirectional | USB Data Signal Plus. |
| 9 | VPLL | power_in | +3.3V input for the internal PHY PLL; LC filtering is recommended. |
| 10 | TEST | input | IC test pin; connect to GND for normal operation. |
| 11 | RESET# | input | Active-low reset input; tie to VCCIO (+3.3V) if not used. |
| 12 | ADBUS0 | bidirectional | Channel A bit 0: TXD in UART mode, D0 in bit-bang, TCK/SK in MPSSE. |
| 13 | ADBUS1 | bidirectional | Channel A bit 1: RXD in UART mode, D1 in bit-bang, TDI/DO in MPSSE. |
| 14 | ADBUS2 | bidirectional | Channel A bit 2: RTS# in UART mode, D2 in bit-bang, TDO/DI in MPSSE. |
| 15 | ADBUS3 | bidirectional | Channel A bit 3: CTS# in UART mode, D3 in bit-bang, TMS/CS in MPSSE. |
| 16 | VCCIO | power_in | +3.3V I/O interface supply input; all VCCIO pins must be connected or the device fails. |
| 17 | ADBUS4 | bidirectional | Channel A bit 4: DTR# in UART mode, D4 in bit-bang, GPIOL0 in MPSSE. |
| 18 | ADBUS5 | bidirectional | Channel A bit 5: DSR# in UART mode, D5 in bit-bang, GPIOL1 in MPSSE. |
| 19 | ADBUS6 | bidirectional | Channel A bit 6: DCD# in UART mode, D6 in bit-bang, GPIOL2 in MPSSE. |
| 20 | ADBUS7 | bidirectional | Channel A bit 7: RI# or TXDEN (EEPROM-selectable, default RI#) in UART mode, D7 in bit-bang, GPIOL3 in MPSSE. |
| 21 | GND | power_in | 0V ground input. |
| 22 | BDBUS0 | bidirectional | Channel B bit 0: TXD in UART mode, D0 in bit-bang, TCK/SK in MPSSE. |
| 23 | BDBUS1 | bidirectional | Channel B bit 1: RXD in UART mode, D1 in bit-bang, TDI/DO in MPSSE. |
| 24 | BDBUS2 | bidirectional | Channel B bit 2: RTS# in UART mode, D2 in bit-bang, TDO/DI in MPSSE. |
| 25 | BDBUS3 | bidirectional | Channel B bit 3: CTS# in UART mode, D3 in bit-bang, TMS/CS in MPSSE. |
| 26 | BDBUS4 | bidirectional | Channel B bit 4: DTR# in UART mode, D4 in bit-bang, GPIOL0 in MPSSE. |
| 27 | BDBUS5 | bidirectional | Channel B bit 5: DSR# in UART mode, D5 in bit-bang, GPIOL1 in MPSSE. |
| 28 | BDBUS6 | bidirectional | Channel B bit 6: DCD# in UART mode, D6 in bit-bang, GPIOL2 in MPSSE. |
| 29 | BDBUS7 | bidirectional | Channel B bit 7: RI# or TXDEN (EEPROM-selectable, default RI#) in UART mode, D7 in bit-bang, GPIOL3 in MPSSE. |
| 30 | SUSPEND# | output | Active low when USB is in suspend mode. |
| 31 | VCORE | power_in | +1.8V core supply voltage input. |
| 32 | CDBUS0 | bidirectional | Channel C bit 0: TXD in UART mode, D0 in bit-bang. |
| 33 | CDBUS1 | bidirectional | Channel C bit 1: RXD in UART mode, D1 in bit-bang. |
| 34 | CDBUS2 | bidirectional | Channel C bit 2: RTS# in UART mode, D2 in bit-bang. |
| 35 | CDBUS3 | bidirectional | Channel C bit 3: CTS# in UART mode, D3 in bit-bang. |
| 36 | VCCIO | power_in | +3.3V I/O interface supply input; all VCCIO pins must be connected or the device fails. |
| 37 | CDBUS4 | bidirectional | Channel C bit 4: DTR# in UART mode, D4 in bit-bang. |
| 38 | CDBUS5 | bidirectional | Channel C bit 5: DSR# in UART mode, D5 in bit-bang. |
| 39 | CDBUS6 | bidirectional | Channel C bit 6: DCD# in UART mode, D6 in bit-bang. |
| 40 | CDBUS7 | bidirectional | Channel C bit 7: RI# or TXDEN (EEPROM-selectable, default RI#) in UART mode, D7 in bit-bang. |
| 41 | GND | power_in | 0V ground input. |
| 42 | DDBUS0 | bidirectional | Channel D bit 0: TXD in UART mode, D0 in bit-bang. |
| 43 | VREGOUT | power_out | +1.8V integrated regulator output; connect to VCORE with a 3.3uF filter capacitor. |
| 44 | VREGIN | power_in | +3.3V input to the integrated 1.8V voltage regulator. |
| 45 | GND | power_in | 0V ground input. |
| 46 | DDBUS1 | bidirectional | Channel D bit 1: RXD in UART mode, D1 in bit-bang. |
| 47 | DDBUS2 | bidirectional | Channel D bit 2: RTS# in UART mode, D2 in bit-bang. |
| 48 | DDBUS3 | bidirectional | Channel D bit 3: CTS# in UART mode, D3 in bit-bang. |
| 49 | DDBUS4 | bidirectional | Channel D bit 4: DTR# in UART mode, D4 in bit-bang. |
| 50 | VCCIO | power_in | +3.3V I/O interface supply input; all VCCIO pins must be connected or the device fails. |
| 51 | DDBUS5 | bidirectional | Channel D bit 5: DSR# in UART mode, D5 in bit-bang. |
| 52 | DDBUS6 | bidirectional | Channel D bit 6: DCD# in UART mode, D6 in bit-bang. |
| 53 | DDBUS7 | bidirectional | Channel D bit 7: RI# or TXDEN (EEPROM-selectable, default RI#) in UART mode, D7 in bit-bang. |
| 54 | PWREN# | output | Active-low power-enable output: 0 = normal operation, 1 = USB suspend or device not configured. |
| 55 | EEDATA | bidirectional | EEPROM data I/O; connect directly to EEPROM Data-In and to Data-Out via 2.2K, with Data-Out pulled to VCC via 10K; tri-state during reset. |
| 56 | EECLK | output | Clock signal to EEPROM; tri-state during device reset. |
| 57 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | FTDI |
| Package | QFN-56-EP(8x8) |
| Category | Interface ICs |
| Pins | 57 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCORE Operating Supply Voltage | VCORE | 1.62 | 1.8 | 1.98 | V | 25 | |
| VCCIO Operating Supply Voltage | VCCIO | 2.97 | 3.3 | 3.63 | V | Cells are 5V tolerant | 25 |
| Voltage regulator input | VREGIN | 3 | 3.3 | 3.6 | V | 25 | |
| Voltage regulator output | VREGOUT | 1.71 | 1.8 | 1.89 | V | 25 | |
| Regulator Current | Ireg | 150 | mA | VREGIN +3.3V | 25 | ||
| PHY Operating Supply Voltage | VPHY, VPLL | 3 | 3.3 | 3.6 | V | 3.3V I/O | 26 |
| PHY Operating Supply Current | Iccphy | 30 | 60 | mA | High-speed operation at 480 MHz | 26 | |
| PHY Operating Supply Current (suspend) | Iccphy (susp) | 10 | 50 | μA | USB Suspend | 26 | |
| Core Suspend Supply Current | Icc1s | 500 | µA | VCORE = +1.8V USB Suspend | 25 | ||
| Output Voltage High | Voh | 2.4 | 3.14 | V | Ioh = +/-2mA, I/O Drive strength = 4mA | 26 | |
| Output Voltage Low | Vol | 0.18 | 0.4 | V | Iol = +/-2mA, I/O Drive strength = 4mA | 26 | |
| Input low Switching Threshold | Vil | 0.8 | V | LVTTL | 26 | ||
| Input High Switching Threshold | Vih | 2 | V | LVTTL | 26 | ||
| Schmitt trigger negative going threshold voltage | Vt- | 0.8 | 1.1 | V | 26 | ||
| Schmitt trigger positive going threshold voltage | Vt+ | 1.6 | 2 | V | 26 | ||
| Input pull-up resistance | Rpu | 40 | 75 | 190 | KΩ | Vin = 0 | 26 |
| Input pull-down resistance | Rpd | 40 | 75 | 190 | KΩ | Vin =VCCIO | 26 |
| Input Leakage Current | Iin | 15 | 45 | 85 | μA | Vin = 0 | 26 |
| Tri-state output leakage current | Ioz | -10 | 10 | μA | Vin = 5.5V or 0 | 26 | |
| PHY I/O Output Voltage Low | Vol | 0.2 | V | 27 | |||
| PHY I/O Input low Switching Threshold | Vil | 0.8 | V | 27 | |||
| PHY I/O Input High Switching Threshold | Vih | 2 | V | 27 | |||
| OSCI Input Voltage | Vin | 2.97 | 3.3 | 3.63 | V | 32 | |
| OSCI Input Frequency tolerance | FIn | -30 | 30 | ppm | 12 MHz +/- 30ppm | 32 | |
| OSCI Cycle to cycle jitter | Ji | 150 | pS | 32 | |||
| OSCI Input Frequency | FIn | 12 | MHz | 32 | |||
| Storage Temperature | -65 | 150 | °C | 25 | |||
| Ambient Operating Temperature | -40 | 85 | °C | Power Applied | 25 | ||
| VCORE Supply Voltage | VCORE | -0.3 | 2 | V | 25 | ||
| VCCIO IO Voltage | VCCIO | -0.3 | 4 | V | 25 | ||
| DC Input Voltage, USBDP and USBDM | -0.5 | 3.63 | V | 25 | |||
| DC Input Voltage, High Impedance Bi-directional | -0.3 | 5.8 | V | powered from VCCIO | 25 | ||
| DC Input Voltage, All Other Inputs | -0.5 | V | max = VCCIO + 0.5 V | 25 | |||
| DC Output Current, Outputs | 16 | mA | 25 | ||||
| Junction Temperature | TJ | -40 | 25 | 125 | °C | FT4232HL/FT4232HQ | 27 |
| Core Operating Supply Current | Icc1 | 70 | mA | VCORE = +1.8V Normal Operation | 25 | ||
| Core Reset Supply Current | Icc1r | 5 | mA | VCORE = +1.8V Device in reset state. | 25 |
CAD (KiCad official)
- Symbol:
FT4232H-56Q-TRAY - Footprint:
Package_DFN_QFN:QFN-56-1EP_8x8mm_P0.5mm_EP4.5x5.2mm - 3D model: QFN-56-EP(8x8) (KiCad packages3D, STEP)
- 3D model files:
ft4232h-56q-tray-etched.step/ft4232h-56q-tray-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ft4232h-56q-tray.step/ft4232h-56q-tray.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: FTDI datasheet (45 pp, sha256
19462d37a9d1e484, retrieved 2026-10-27, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).