component
FT3107T
Public Made by Adomby adom
Fortior Tech Brushed DC Motor Drivers, TSSOP-20. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
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FT3107T
Fortior Tech · Brushed DC Motor Drivers · TSSOP-20
FT3107T from Fortior Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS | power_in | Signal and power ground for the controller. |
| 2 | VDD5 | power_out | Digital 5 V LDO output for the digital signal circuitry, specified at 4.9 V to 5.1 V with up to 10 mA output current. |
| 3 | TM | input | Test pin that should be left floating or connected to VDD5. |
| 4 | BRAKE | input | Brake signal input where a low level brakes the motor, with an internal pull-up of 50 kΩ to 150 kΩ (100 kΩ typical). |
| 5 | SPEED/PWM | input | Speed control input accepting either a direct PWM signal (1 kHz to 60 kHz) or an analog voltage in the 0 V to 5.3 V range. |
| 6 | FR | input | Motor rotation direction input. |
| 7 | ILIMIT | input | Current limit analog input, specified for an analog input range of 0 V to 5.3 V when used as the VREF source. |
| 8 | FG | output | Open-drain Frequency Generator speed signal output that requires an external pull-up, with a maximum output current of 10 mA and a maximum withstand voltage of 5.5 V. |
| 9 | EMF_W | input | Phase W back-EMF input that must be proportionately stepped down to less than VDD5 for IC protection. |
| 10 | EMF_V | input | Phase V back-EMF input that must be proportionately stepped down to less than VDD5 for IC protection. |
| 11 | EMF_U | input | Phase U back-EMF input that must be proportionately stepped down to less than VDD5 for IC protection. |
| 12 | ISENSE | input | Current limit and lead angle analog input, where 0 V to 5 V sets a lead angle of 0° to 15°. |
| 13 | WL | output | Low-side phase W NMOS gate driver output, with output high of 8.5 V to 11 V and output low of 0 V to 0.3 V. |
| 14 | VL | output | Low-side phase V NMOS gate driver output, with output high of 8.5 V to 11 V and output low of 0 V to 0.3 V. |
| 15 | UL | output | Low-side phase U NMOS gate driver output, with output high of 8.5 V to 11 V and output low of 0 V to 0.3 V. |
| 16 | WH | output | High-side phase W PMOS driver output, with output high of 11.2 V to 12 V and output low of 3 V to 5 V. |
| 17 | VH | output | High-side phase V PMOS driver output, with output high of 11.2 V to 12 V and output low of 3 V to 5 V. |
| 18 | UH | output | High-side phase U PMOS driver output, with output high of 11.2 V to 12 V and output low of 3 V to 5 V. |
| 19 | VREG10 | power_out | 10 V LDO output, specified at 9.5 V to 10.5 V with up to 10 mA output current. |
| 20 | VCC | power_in | Power supply input, with a recommended range of 3.7 V to 28 V and an absolute maximum of 30 V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Fortior Tech |
| Package | TSSOP-20 |
| Category | Motor Driver ICs |
| Pins | 20 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage (absolute maximum) | Vccmax | 30 | V | 3 | |||
| FG output current (absolute maximum) | IFGmax | 10 | mA | 3 | |||
| FG output pin withstand voltage (absolute maximum) | VFG max | 5.5 | V | 3 | |||
| Operating temperature | Topr | -40 | 125 | ℃ | 3 | ||
| Storage temperature | Tstg | -65 | 150 | ℃ | 3 | ||
| Package thermal resistance, junction to ambient (4-layer PCB, JEDEC) | Rθja | 100 | ℃/W | 4-layer PCB based on JEDEC standard | 3 | ||
| Power supply voltage (recommended operating) | Vcc | 3.7 | 12 | 28 | V | 3 | |
| Power supply current | Icc | 8 | 15 | mA | Working | 4 | |
| VDD5 LDO regulator voltage | VDD5 | 4.9 | 5 | 5.1 | V | 4 | |
| VDD5 regulator output current | Iv5out | 10 | mA | VDD5=5V | 4 | ||
| 10V regulator voltage | Vreg10 | 9.5 | 10 | 10.5 | V | 4 | |
| 10V regulator output current | Iv10out | 10 | mA | Vreg10=10V | 4 | ||
| Analog input range | 0 | 5.3 | V | 4 | |||
| High-level input voltage | Vdinh | 2.5 | 5.3 | V | 4 | ||
| Low-level input voltage | Vdinl | 0 | 2 | V | 4 | ||
| Internal pull-up resistor | Rdio | 50 | 100 | 150 | kohm | 4 | |
| PWM input frequency | Fpwm | 1 | 60 | kHz | 4 | ||
| High side PMOS driver output high voltage | HVoh | 11.2 | 11.5 | 12 | V | Sink current = 20mA | 4 |
| High side PMOS driver output low voltage | HVol | 3 | 5 | V | Source current = 20mA | 4 | |
| High side PMOS driver source current | Io+ | 150 | mA | 4 | |||
| High side PMOS driver sink current | Io- | 90 | mA | 4 | |||
| Low side NMOS driver output high voltage | LVoh | 8.5 | 10 | 11 | V | Sink current = 20mA | 4 |
| Low side NMOS driver output low voltage | LVol | 0 | 0.3 | V | Source current = 20mA | 4 | |
| Low side NMOS driver source current | Io+ | 150 | mA | 4 | |||
| Low side NMOS driver sink current | Io- | 180 | mA | 4 | |||
| FG output pin low-level voltage | VFG | 0.1 | 0.2 | V | When Io=5mA | 4 | |
| Thermal protection circuit operating temperature | TSD | 150 | ℃ | Design target | 4 | ||
| Temperature hysteresis width | △TSD | 30 | ℃ | Design target | 4 |
CAD (KiCad official)
- Symbol:
FT3107T - Footprint:
Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm - 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files:
ft3107t-etched.step/ft3107t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ft3107t.step/ft3107t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: Fortior Tech datasheet (11 pp, sha256
935a11adc91257fd, retrieved 2026-10-18, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# FT3107T
**Fortior Tech** · Brushed DC Motor Drivers · TSSOP-20
FT3107T from Fortior Tech, in a TSSOP-20. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | VSS | power_in | Signal and power ground for the controller. |
| 2 | VDD5 | power_out | Digital 5 V LDO output for the digital signal circuitry, specified at 4.9 V to 5.1 V with up to 10 mA output current. |
| 3 | TM | input | Test pin that should be left floating or connected to VDD5. |
| 4 | BRAKE | input | Brake signal input where a low level brakes the motor, with an internal pull-up of 50 kΩ to 150 kΩ (100 kΩ typical). |
| 5 | SPEED/PWM | input | Speed control input accepting either a direct PWM signal (1 kHz to 60 kHz) or an analog voltage in the 0 V to 5.3 V range. |
| 6 | FR | input | Motor rotation direction input. |
| 7 | ILIMIT | input | Current limit analog input, specified for an analog input range of 0 V to 5.3 V when used as the VREF source. |
| 8 | FG | output | Open-drain Frequency Generator speed signal output that requires an external pull-up, with a maximum output current of 10 mA and a maximum withstand voltage of 5.5 V. |
| 9 | EMF_W | input | Phase W back-EMF input that must be proportionately stepped down to less than VDD5 for IC protection. |
| 10 | EMF_V | input | Phase V back-EMF input that must be proportionately stepped down to less than VDD5 for IC protection. |
| 11 | EMF_U | input | Phase U back-EMF input that must be proportionately stepped down to less than VDD5 for IC protection. |
| 12 | ISENSE | input | Current limit and lead angle analog input, where 0 V to 5 V sets a lead angle of 0° to 15°. |
| 13 | WL | output | Low-side phase W NMOS gate driver output, with output high of 8.5 V to 11 V and output low of 0 V to 0.3 V. |
| 14 | VL | output | Low-side phase V NMOS gate driver output, with output high of 8.5 V to 11 V and output low of 0 V to 0.3 V. |
| 15 | UL | output | Low-side phase U NMOS gate driver output, with output high of 8.5 V to 11 V and output low of 0 V to 0.3 V. |
| 16 | WH | output | High-side phase W PMOS driver output, with output high of 11.2 V to 12 V and output low of 3 V to 5 V. |
| 17 | VH | output | High-side phase V PMOS driver output, with output high of 11.2 V to 12 V and output low of 3 V to 5 V. |
| 18 | UH | output | High-side phase U PMOS driver output, with output high of 11.2 V to 12 V and output low of 3 V to 5 V. |
| 19 | VREG10 | power_out | 10 V LDO output, specified at 9.5 V to 10.5 V with up to 10 mA output current. |
| 20 | VCC | power_in | Power supply input, with a recommended range of 3.7 V to 28 V and an absolute maximum of 30 V. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | Fortior Tech |
| Package | TSSOP-20 |
| Category | Motor Driver ICs |
| Pins | 20 |
## Electrical characteristics
Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Power supply voltage (absolute maximum) | Vccmax | | | 30 | V | | 3 |
| FG output current (absolute maximum) | IFGmax | | | 10 | mA | | 3 |
| FG output pin withstand voltage (absolute maximum) | VFG max | | | 5.5 | V | | 3 |
| Operating temperature | Topr | -40 | | 125 | ℃ | | 3 |
| Storage temperature | Tstg | -65 | | 150 | ℃ | | 3 |
| Package thermal resistance, junction to ambient (4-layer PCB, JEDEC) | Rθja | | 100 | | ℃/W | 4-layer PCB based on JEDEC standard | 3 |
| Power supply voltage (recommended operating) | Vcc | 3.7 | 12 | 28 | V | | 3 |
| Power supply current | Icc | | 8 | 15 | mA | Working | 4 |
| VDD5 LDO regulator voltage | VDD5 | 4.9 | 5 | 5.1 | V | | 4 |
| VDD5 regulator output current | Iv5out | 10 | | | mA | VDD5=5V | 4 |
| 10V regulator voltage | Vreg10 | 9.5 | 10 | 10.5 | V | | 4 |
| 10V regulator output current | Iv10out | 10 | | | mA | Vreg10=10V | 4 |
| Analog input range | | 0 | | 5.3 | V | | 4 |
| High-level input voltage | Vdinh | 2.5 | | 5.3 | V | | 4 |
| Low-level input voltage | Vdinl | 0 | | 2 | V | | 4 |
| Internal pull-up resistor | Rdio | 50 | 100 | 150 | kohm | | 4 |
| PWM input frequency | Fpwm | 1 | | 60 | kHz | | 4 |
| High side PMOS driver output high voltage | HVoh | 11.2 | 11.5 | 12 | V | Sink current = 20mA | 4 |
| High side PMOS driver output low voltage | HVol | | 3 | 5 | V | Source current = 20mA | 4 |
| High side PMOS driver source current | Io+ | | 150 | | mA | | 4 |
| High side PMOS driver sink current | Io- | | 90 | | mA | | 4 |
| Low side NMOS driver output high voltage | LVoh | 8.5 | 10 | 11 | V | Sink current = 20mA | 4 |
| Low side NMOS driver output low voltage | LVol | | 0 | 0.3 | V | Source current = 20mA | 4 |
| Low side NMOS driver source current | Io+ | | 150 | | mA | | 4 |
| Low side NMOS driver sink current | Io- | | 180 | | mA | | 4 |
| FG output pin low-level voltage | VFG | | 0.1 | 0.2 | V | When Io=5mA | 4 |
| Thermal protection circuit operating temperature | TSD | | 150 | | ℃ | Design target | 4 |
| Temperature hysteresis width | △TSD | | 30 | | ℃ | Design target | 4 |
## CAD (KiCad official)
- Symbol: `FT3107T`
- Footprint: `Package_SO:TSSOP-20_4.4x6.5mm_P0.65mm`
- 3D model: TSSOP-20 (KiCad packages3D, STEP)
- 3D model files: `ft3107t-etched.step` / `ft3107t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ft3107t.step` / `ft3107t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [Fortior Tech datasheet](https://jlcpcb.com/api/file/downloadByFileSystemAccessId/8588908711578779648) (11 pp, sha256 `935a11adc91257fd`, retrieved 2026-10-18, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ft3107t-datasheet.pdf)