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FT24C64A-ESR-T
Public Made by Adomby adom
FMD Fremont Micro Devices EEPROM, SOP-8. Pinout extracted from the datasheet, KiCad symbol/footprint/3D.
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FT24C64A-ESR-T
FMD Fremont Micro Devices · EEPROM · SOP-8
FT24C64A-ESR-T from FMD Fremont Micro Devices, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input bit 0. Hardwire to VIH or VIL to set the chip select address; internally recognized as VIL if left unconnected. |
| 2 | A1 | input | Device address input bit 1. Hardwire to VIH or VIL to set the chip select address; internally recognized as VIL if left unconnected. |
| 3 | A2 | input | Device address input bit 2. Hardwire to VIH or VIL to set the chip select address; internally recognized as VIL if left unconnected. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Serial data line. Bi-directional open-drain I/O for I2C data; requires external pull-up (typ. 1.3 kOhm to VCC per AC test conditions) and can be wire-OR'd with other open-drain devices. |
| 6 | SCL | input | Serial clock input. Data is latched on the rising edge and clocked out on the falling edge. Up to 1 MHz at 2.5-5V VCC, 400 kHz at 1.8V VCC. |
| 7 | WP | input | Write protect input. Programming is allowed when WP is unconnected or tied to VIL; all programming is disabled when WP is tied to VIH or VCC. Read operations are unaffected by WP. |
| 8 | VCC | power_in | Supply voltage, 1.8V to 5.5V. Absolute maximum 8V. Typical read/write current 0.4 mA / 2.0 mA at 5.0V; standby current <1 uA. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | FMD Fremont Micro Devices |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
Ordering variants
Same part, different packaging or reel option.
FT24C64A-ESR-BFT24C64A-ESR-TFT24C64A-ESR-TESG-BFT24C64A-ESR-TESG-TFT24C64A-ESR-TEDR-BFT24C64A-ESR-TEDG-BFT24C64A-ESR-TEMR-BFT24C64A-ESR-TEMR-TFT24C64A-ESR-TEMG-BFT24C64A-ESR-TEMG-TFT24C64A-ESR-TETR-BFT24C64A-ESR-TETR-TFT24C64A-ESR-TETG-BFT24C64A-ESR-TETG-TFT24C64A-ESR-TENR-TFT24C64A-ESR-TENG-TFT24C64A-ESR-TELR-TFT24C64A-ESR-TELG-TFT24C64A-ESR-TEPR-TFT24C64A-ESR-TEPG-T
CAD (KiCad official)
- Symbol:
FT24C64A-ESR-T - Footprint:
Package_SO:SOIC-8_3.9x4.9mm_P1.27mm - 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files:
ft24c64a-esr-t-etched.step/ft24c64a-esr-t-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ft24c64a-esr-t.step/ft24c64a-esr-t.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: FMD Fremont Micro Devices datasheet (18 pp, sha256
8fe866cc9ddfd87f, retrieved 2026-08-17, tier: lcsc) - Extractor:
ds2sf(Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate. - CAD: KiCad official libraries (CC-BY-SA 4.0).
# FT24C64A-ESR-T
**FMD Fremont Micro Devices** · EEPROM · SOP-8
FT24C64A-ESR-T from FMD Fremont Micro Devices, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet by ds2sf; symbol, footprint, and 3D from KiCad-official CAD.
## Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input bit 0. Hardwire to VIH or VIL to set the chip select address; internally recognized as VIL if left unconnected. |
| 2 | A1 | input | Device address input bit 1. Hardwire to VIH or VIL to set the chip select address; internally recognized as VIL if left unconnected. |
| 3 | A2 | input | Device address input bit 2. Hardwire to VIH or VIL to set the chip select address; internally recognized as VIL if left unconnected. |
| 4 | GND | power_in | Ground reference for the device. |
| 5 | SDA | bidirectional | Serial data line. Bi-directional open-drain I/O for I2C data; requires external pull-up (typ. 1.3 kOhm to VCC per AC test conditions) and can be wire-OR'd with other open-drain devices. |
| 6 | SCL | input | Serial clock input. Data is latched on the rising edge and clocked out on the falling edge. Up to 1 MHz at 2.5-5V VCC, 400 kHz at 1.8V VCC. |
| 7 | WP | input | Write protect input. Programming is allowed when WP is unconnected or tied to VIL; all programming is disabled when WP is tied to VIH or VCC. Read operations are unaffected by WP. |
| 8 | VCC | power_in | Supply voltage, 1.8V to 5.5V. Absolute maximum 8V. Typical read/write current 0.4 mA / 2.0 mA at 5.0V; standby current <1 uA. |
## Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | FMD Fremont Micro Devices |
| Package | SOP-8 |
| Category | Memory |
| Pins | 8 |
## Ordering variants
Same part, different packaging or reel option.
- `FT24C64A-ESR-B`
- `FT24C64A-ESR-T`
- `FT24C64A-ESR-TESG-B`
- `FT24C64A-ESR-TESG-T`
- `FT24C64A-ESR-TEDR-B`
- `FT24C64A-ESR-TEDG-B`
- `FT24C64A-ESR-TEMR-B`
- `FT24C64A-ESR-TEMR-T`
- `FT24C64A-ESR-TEMG-B`
- `FT24C64A-ESR-TEMG-T`
- `FT24C64A-ESR-TETR-B`
- `FT24C64A-ESR-TETR-T`
- `FT24C64A-ESR-TETG-B`
- `FT24C64A-ESR-TETG-T`
- `FT24C64A-ESR-TENR-T`
- `FT24C64A-ESR-TENG-T`
- `FT24C64A-ESR-TELR-T`
- `FT24C64A-ESR-TELG-T`
- `FT24C64A-ESR-TEPR-T`
- `FT24C64A-ESR-TEPG-T`
## CAD (KiCad official)
- Symbol: `FT24C64A-ESR-T`
- Footprint: `Package_SO:SOIC-8_3.9x4.9mm_P1.27mm`
- 3D model: SOP-8 (KiCad packages3D, STEP)
- 3D model files: `ft24c64a-esr-t-etched.step` / `ft24c64a-esr-t-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ft24c64a-esr-t.step` / `ft24c64a-esr-t.glb` are the bare package body.
## Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- **Datasheet:** [FMD Fremont Micro Devices datasheet](docs/ft24c64a-esr-t-datasheet.pdf) (18 pp, sha256 `8fe866cc9ddfd87f`, retrieved 2026-08-17, tier: lcsc)
- **Extractor:** `ds2sf` (Claude). Every pin and dimension is cited to a datasheet page; it refuses to fabricate.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).
[Datasheet PDF](docs/ft24c64a-esr-t-datasheet.pdf)