component
FT24C64A-EDR-B
Public Made by Adomby adom
FMD(Fremont Micro Devices) EEPROM, DIP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownFT24C64A-EDR-B
FMD(Fremont Micro Devices) · EEPROM · DIP-8
FT24C64A-EDR-B from FMD(Fremont Micro Devices), in a DIP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | A0 | input | Device address input that is hardwired to VIH or VIL and is recognized as VIL if left unconnected. |
| 2 | A1 | input | Device address input that is hardwired to VIH or VIL and is recognized as VIL if left unconnected. |
| 3 | A2 | input | Device address input that is hardwired to VIH or VIL and is recognized as VIL if left unconnected. |
| 4 | GND | power_in | Ground. |
| 5 | SDA | bidirectional | Serial data input and open-drain output that can be wired-OR with other open-drain devices and is typically pulled high by an external resistor. |
| 6 | SCL | input | Serial clock input where the rising edge latches data into the EEPROM and the falling edge clocks data out. |
| 7 | WP | input | Write protect input that disables all programming when connected to VIH or VCC and allows programming when left unconnected or at VIL; reads are unaffected. |
| 8 | VCC | power_in | Power supply, 1.8V to 5.5V. |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | FMD(Fremont Micro Devices) |
| Package | DIP-8 |
| Category | Memory |
| Pins | 8 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | -50 | 125 | °C | 2 | |||
| Industrial operating temperature | -40 | 85 | °C | 2 | |||
| Input voltage on any pin relative to ground | -0.3 | V | relative to ground; printed maximum is VCC + 0.3V | 2 | |||
| Maximum voltage | 8 | V | 2 | ||||
| ESD protection on all pins | 2000 | V | on all pins; printed as >2000V | 2 | |||
| 24C××A supply voltage | VCC | 1.8 | 5.5 | V | 9 | ||
| Supply read current | ICC | 0.4 | 1 | mA | VCC @ 5.0V, SCL = 400 kHz | 9 | |
| Supply write current | ICC | 2 | 3 | mA | VCC @ 5.0V, SCL = 400 kHz | 9 | |
| Supply current | ISB1 | 1 | µA | VCC @ 1.8V, VIN = VCC or VSS | 9 | ||
| Input leakage current | IIL | 3 | µA | VIN = VCC or VSS | 9 | ||
| Output leakage current | ILO | 3 | µA | VIN = VCC or VSS | 9 | ||
| Input low level | VIL | -0.6 | V | printed maximum is VCC × 0.3 | 9 | ||
| Output low level | VOL2 | 0.4 | V | VCC @ 3.0V, IOL = 2.1 mA | 9 | ||
| Output low level | VOL1 | 0.2 | V | VCC @ 1.8V, IOL = 0.15 mA | 9 | ||
| Clock frequency, SCL | fSCL | 400 | kHz | 1.8V | 8 | ||
| Clock frequency, SCL | fSCL | 1000 | kHz | 2.5-5.0 V | 8 | ||
| Clock pulse width low | tLOW | 1.2 | µs | 1.8V | 8 | ||
| Clock pulse width low | tLOW | 0.6 | µs | 2.5-5.0 V | 8 | ||
| Clock pulse width high | tHIGH | 0.4 | µs | 1.8V | 8 | ||
| Clock pulse width high | tHIGH | 0.3 | µs | 2.5-5.0 V | 8 | ||
| Noise suppression time | tI | 120 | ns | 1.8V | 8 | ||
| Clock low to data out valid | tAA | 0.3 | 1.2 | µs | 1.8V | 8 | |
| Clock low to data out valid | tAA | 0.2 | 0.5 | µs | 2.5-5.0 V | 8 | |
| Bus free time before new transmission | tBUF | 1.3 | µs | 1.8V | 8 | ||
| Bus free time before new transmission | tBUF | 1.2 | µs | 2.5-5.0 V | 8 | ||
| START hold time | tHD.STA | 0.6 | µs | 1.8V | 8 | ||
| START set-up time | tSU.STA | 0.6 | µs | 1.8V | 8 | ||
| Data in hold time | tHD.DAT | 0 | µs | 1.8V | 8 | ||
| Data in set-up time | tSU.DAT | 100 | ns | 1.8V | 8 | ||
| Input rise time | tR | 300 | ns | 8 | |||
| Input fall time | tF | 300 | ns | 8 | |||
| STOP set-up time | tSU.STO | 0.6 | µs | 1.8V | 8 | ||
| Data out hold time | tDH | 200 | ns | 1.8V | 8 | ||
| Data out hold time | tDH | 50 | ns | 2.5-5.0 V | 8 | ||
| Write cycle time | tWR | 5 | ms | 8 | |||
| Endurance | 1e+06 | Write Cycles | 25°C, Page Mode, 3.3V | 8 |
CAD (KiCad official)
- Symbol:
FT24C64A-EDR-B - Footprint:
Package_DIP:DIP-8_W7.62mm - 3D model: DIP-8 (KiCad packages3D, STEP)
- 3D model files:
ft24c64a-edr-b-etched.step/ft24c64a-edr-b-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ft24c64a-edr-b.step/ft24c64a-edr-b.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: FMD(Fremont Micro Devices) datasheet (19 pp, sha256
2dbcc2b9411353b5, retrieved 2026-10-20, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-sonnet-5-5(text+vision), consensusclaude-opus-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).