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FT24C32A-ESR-B

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FMD Fremont Micro Devices EEPROM, SOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FT24C32A-ESR-B

FMD Fremont Micro Devices · EEPROM · SOP-8

FT24C32A-ESR-B from FMD Fremont Micro Devices, in a SOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Device address input that is hardwired to VIH or VIL and is read as VIL if left unconnected, though connecting it to a known state is recommended.
2 A1 input Device address input that is hardwired to VIH or VIL and is read as VIL if left unconnected, though connecting it to a known state is recommended.
3 A2 input Device address input that is hardwired to VIH or VIL and is read as VIL if left unconnected, though connecting it to a known state is recommended.
4 GND power_in Ground.
5 SDA bidirectional Serial data line, bi-directional with an open-drain output that can be wired-OR with other open-drain devices and is typically pulled high by an external resistor.
6 SCL input Serial clock input where the rising edge latches data into the EEPROM and the falling edge clocks data out.
7 WP input Write protect input that disables all programming when connected to VIH or VCC, allows programming when left unconnected or at VIL, and does not affect reads.
8 VCC power_in Power supply, 1.8V to 5.5V, with a decoupling capacitor of at least 10nF recommended.

Key specifications

Parameter Value
Manufacturer FMD Fremont Micro Devices
Package SOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Storage temperature -50 125 ℃ 2
Industrial operating temperature -40 85 ℃ 2
Maximum voltage 8 V 2
Input voltage on any pin relative to ground -0.3 V relative to ground; upper limit printed as VCC + 0.3V, not numeric 2
ESD protection on all pins 2000 V all pins; printed as >2000V 2
Supply voltage VCC VCC1 1.8 5.5 V 11
Supply read current ICC1 0.4 1 mA VCC @ 5.0V, SCL = 400 kHz 11
Supply write current ICC2 2 3 mA VCC @ 5.0V, SCL = 400 kHz 11
Supply current ISB1 1 µA VCC @ 1.8V, VIN = VCC or VSS 11
Input leakage current IIL 3 µA VIN = VCC or VSS 11
Output leakage current ILO 3 µA VIN = VCC or VSS 11
Input low level VIL -0.6 V upper limit printed as VCC×0.3, not numeric 11
Output low level VOL2 0.4 V VCC @ 3.0V, IOL = 2.1 mA 11
Output low level VOL1 0.2 V VCC @ 1.8V, IOL = 0.15 mA 11
Clock frequency, SCL fSCL 400 kHz VCC 1.8V 10
Clock frequency, SCL fSCL 1000 kHz VCC 2.5V-5.5V 10
Clock pulse width low tLOW 1.3 µs VCC 1.8V 10
Clock pulse width low tLOW 0.4 µs VCC 2.5V-5.5V 10
Clock pulse width high tHIGH 0.6 µs VCC 1.8V 10
Clock pulse width high tHIGH 0.4 µs VCC 2.5V-5.5V 10
Noise suppression time tI 50 ns VCC 1.8V; footnote 1 (characterized, not screened) 10
Clock low to data out valid tAA 0.2 0.9 µs VCC 1.8V 10
Clock low to data out valid tAA 0.2 0.55 µs VCC 2.5V-5.5V 10
Time the bus must be free before a new transmission can start tBUF 1.3 µs VCC 1.8V; footnote 1 10
Time the bus must be free before a new transmission can start tBUF 0.5 µs VCC 2.5V-5.5V; footnote 1 10
START hold time tHD.STA 0.6 µs VCC 1.8V 10
START hold time tHD.STA 0.25 µs VCC 2.5V-5.5V 10
START set-up time tSU.STA 0.6 µs VCC 1.8V 10
START set-up time tSU.STA 0.25 µs VCC 2.5V-5.5V 10
Data in hold time tHD.DAT 0 µs VCC 1.8V 10
Data in set-up time tSU.DAT 100 ns VCC 1.8V 10
Input rise time tR 300 ns VCC 1.8V; footnote 1 10
Input fall time tF 300 ns VCC 1.8V; footnote 1 10
STOP set-up time tSU.STO 0.6 µs VCC 1.8V 10
STOP set-up time tSU.STO 0.25 µs VCC 2.5V-5.5V 10
Data out hold time tDH 50 ns VCC 1.8V 10
VCC slew rate at power up tPWR,R 0.1 50 V/ms VCC 1.8V; footnote 1 10
Time required after VCC is stable before the device can accept commands tPUP 100 µs VCC 1.8V; footnote 1 10
Minimum time at Vcc=0V between power cycles tPOFF 500 ms VCC 1.8V; footnote 1 10
Write cycle time tWR 5 ms VCC 1.8V 10
Endurance 1e+06 Write Cycles 25oC, Page Mode, 3.3V; footnote 1 10

CAD (KiCad official)

  • Symbol: FT24C32A-ESR-B
  • Footprint: Package_SO:SOIC-8_3.9x4.9mm_P1.27mm
  • 3D model: SOP-8 (KiCad packages3D, STEP)
  • 3D model files: ft24c32a-esr-b-etched.step / ft24c32a-esr-b-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft24c32a-esr-b.step / ft24c32a-esr-b.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FMD Fremont Micro Devices datasheet (20 pp, sha256 449794ca9d24fd9e, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text+vision), consensus claude-opus-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF