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FT24C128A-ETR-T

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FMD Fremont Micro Devices EEPROM, TSSOP-8. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FT24C128A-ETR-T

FMD Fremont Micro Devices · EEPROM · TSSOP-8

FT24C128A-ETR-T from FMD Fremont Micro Devices, in a TSSOP-8. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 A0 input Device address input used as a chip select; hardwired to VIH or VIL, and internally recognized as VIL if left unconnected.
2 A1 input Device address input used as a chip select; hardwired to VIH or VIL, and internally recognized as VIL if left unconnected.
3 A2 input Device address input used as a chip select; hardwired to VIH or VIL, and internally recognized as VIL if left unconnected.
4 GND power_in Ground reference for the device.
5 SDA bidirectional Serial data line, bi-directional open-drain output that can be wired-OR with other open-drain devices and is typically pulled high by an external resistor.
6 SCL input Serial clock input; the rising edge latches data into the EEPROM and the falling edge clocks data out.
7 WP input Write protect input; programming is allowed when left unconnected or at VIL and all programming is disabled when connected to VIH or VCC, while reads are unaffected.
8 VCC power_in Supply voltage, 1.8V to 5.5V.

Key specifications

Parameter Value
Manufacturer FMD Fremont Micro Devices
Package TSSOP-8
Category Memory
Pins 8

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply voltage VCC1 1.8 5.5 V 24C××A supply 9
Maximum voltage 8 V 2
Storage temperature -50 125 ℃ 2
Industrial operating temperature -40 85 ℃ Industrial operating temperature 2
Input voltage on any pin relative to ground -0.3 V Relative to ground; printed upper limit is VCC + 0.3V 2
ESD protection on all pins 2000 V All pins; printed as >2000V 2
Supply read current ICC 0.4 1 mA VCC @ 5.0V SCL = 100 kHz 9
Supply write current ICC 2 3 mA VCC @ 5.0V SCL = 100 kHz 9
Supply current ISB1 0.02 1 µA VCC @ 1.8V, VIN = VCC or VSS 9
Supply current ISB2 1 µA VCC @ 2.5V, VIN = VCC or VSS 9
Supply current ISB3 0.07 1 µA VCC @ 5.0V, VIN = VCC or VSS 9
Input leakage current IIL 3 µA VIN = VCC or VSS 9
Output leakage current ILO 3 µA VIN = VCC or VSS 9
Input low level VIL -0.6 V Printed upper limit is VCC×0.3 9
Input high level VIH 0.7 ×VCC Printed minimum is VCC×0.7; printed maximum is VCC + 0.5 (not a numeric value in this row) 9
Output low level VOL2 0.4 V VCC @ 3.0V, IOL = 2.1 mA 9
Clock frequency, SCL fSCL 400 kHz VCC 1.8V 8
Clock frequency, SCL fSCL 1000 kHz VCC 2.5-5.0 V 8
Clock pulse width low tLOW 1.3 µs VCC 1.8V 8
Clock pulse width low tLOW 0.4 µs VCC 2.5-5.0 V 8
Clock pulse width high tHIGH 0.6 µs VCC 1.8V 8
Clock pulse width high tHIGH 0.4 µs VCC 2.5-5.0 V 8
Noise suppression time tI 100 ns VCC 1.8V 8
Noise suppression time tI 50 ns VCC 2.5-5.0 V 8
Clock low to data out valid tAA 0.9 µs VCC 1.8V 8
Clock low to data out valid tAA 0.55 µs VCC 2.5-5.0 V 8
Bus free time before new transmission tBUF 1.3 µs VCC 1.8V 8
Bus free time before new transmission tBUF 0.5 µs VCC 2.5-5.0 V 8
START hold time tHD.STA 0.6 µs VCC 1.8V 8
START hold time tHD.STA 0.25 µs VCC 2.5-5.0 V 8
START set-up time tSU.STA 0.6 µs VCC 1.8V 8
START set-up time tSU.STA 0.25 µs VCC 2.5-5.0 V 8
Data in hold time tHD.DAT 0 µs VCC 1.8V 8
Data in set-up time tSU.DAT 100 ns VCC 1.8V 8
Input rise time tR 0.3 µs VCC 1.8V 8
Input fall time tF 300 ns VCC 1.8V 8
Input fall time tF 100 ns VCC 2.5-5.0 V 8
STOP set-up time tSU.STO 0.6 µs VCC 1.8V 8
STOP set-up time tSU.STO 0.25 µs VCC 2.5-5.0 V 8
Data out hold time tDH 50 ns VCC 1.8V 8
Write cycle time tWR 5 ms 8

CAD (KiCad official)

  • Symbol: FT24C128A-ETR-T
  • Footprint: Package_SO:TSSOP-8_3x3mm_P0.65mm
  • 3D model: TSSOP-8 (KiCad packages3D, STEP)
  • 3D model files: ft24c128a-etr-t-etched.step / ft24c128a-etr-t-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft24c128a-etr-t.step / ft24c128a-etr-t.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: FMD Fremont Micro Devices datasheet (16 pp, sha256 8365e4d4ae03832f, retrieved 2026-10-20, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF