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FT232HQ-REEL
Public Made by Adomby adom
FTDI USB ICs, QFN-48-EP(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.
3D Model
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Symbol & Footprint
Schematic Symbol
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PCB Footprint
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Datasheet
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README
markdownFT232HQ-REEL
FTDI · USB ICs · QFN-48-EP(8x8)
FT232HQ-REEL from FTDI, in a QFN-48-EP(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.
Pinout
| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | OSCI | input | Oscillator input; a 12 MHz crystal connects between OSCI and OSCO, or a 12 MHz oscillator drives OSCI with OSCO left unconnected. |
| 2 | OSCO | output | Oscillator output for the 12 MHz crystal, left unconnected when an external 12 MHz oscillator drives OSCI. |
| 3 | VPHY | power_in | +3.3V input for the internal USB PHY; it cannot be connected directly to the USB supply and needs a +3.3V regulator with LC filtering. |
| 4 | AGND | power_in | 0V analog ground input. |
| 5 | REF | input | Current reference that must be connected through a 12 kΩ 1% resistor to GND. |
| 6 | DM | bidirectional | USB Data Signal Minus. |
| 7 | DP | bidirectional | USB Data Signal Plus. |
| 8 | VPLL | power_in | +3.3V input for the internal PLL supply, recommended to be filtered with an LC filter. |
| 9 | AGND | power_in | 0V analog ground input. |
| 10 | GND | power_in | 0V ground input. |
| 11 | GND | power_in | 0V ground input. |
| 12 | VCCIO | power_in | +3.3V I/O interface power supply input. |
| 13 | ADBUS0 | bidirectional | Configurable I/O pin; default function is TXD (asynchronous transmit data output), and it is D0 in FIFO and bit-bang modes. |
| 14 | ADBUS1 | bidirectional | Configurable I/O pin; default function is RXD (asynchronous receive data input), and it is D1 in FIFO and bit-bang modes. |
| 15 | ADBUS2 | bidirectional | Configurable I/O pin; default function is RTS# (handshake output), and it is D2 in FIFO and bit-bang modes. |
| 16 | ADBUS3 | bidirectional | Configurable I/O pin; default function is CTS# (handshake input), and it is D3 in FIFO and bit-bang modes. |
| 17 | ADBUS4 | bidirectional | Configurable I/O pin; default function is DTR# (handshake output), and it is D4 in FIFO and bit-bang modes. |
| 18 | ADBUS5 | bidirectional | Configurable I/O pin; default function is DSR# (handshake input), and it is D5 in FIFO and bit-bang modes. |
| 19 | ADBUS6 | bidirectional | Configurable I/O pin; default function is DCD# (control input), and it is D6 in FIFO and bit-bang modes. |
| 20 | ADBUS7 | bidirectional | Configurable I/O pin; default function is RI# (control input, remote wake-up when enabled), and it is D7 in FIFO and bit-bang modes. |
| 21 | ACBUS0 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 22 | GND | power_in | 0V ground input. |
| 23 | GND | power_in | 0V ground input. |
| 24 | VCCIO | power_in | +3.3V I/O interface power supply input. |
| 25 | ACBUS1 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 26 | ACBUS2 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 27 | ACBUS3 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 28 | ACBUS4 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted, and in FIFO modes it carries the SIWU# input. |
| 29 | ACBUS5 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 30 | ACBUS6 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 31 | ACBUS7 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PD, and it is the PWRSAV# input in the common function group. |
| 32 | ACBUS8 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 33 | ACBUS9 | bidirectional | Configurable ACBUS I/O pin whose function is set in the EEPROM; default is TriSt-PU if no EEPROM is fitted. |
| 34 | RESET# | input | Active-low reset input; it should be tied to VCCIO if not used. |
| 35 | GND | power_in | 0V ground input. |
| 36 | GND | power_in | 0V ground input. |
| 37 | VCCA | power_out | +1.8V output that should not be used externally and must be terminated with a 0.1 µF capacitor to GND. |
| 38 | VCORE | power_out | +1.8V core supply output that should not be used externally and must be terminated with a 0.1 µF capacitor to GND. |
| 39 | VCCD | power_out | +3.3V output when VREGIN is +5.0V, or +3.3V input when VREGIN is 3V3. |
| 40 | VREGIN | power_in | +5.0V or 3V3 power supply input to the on-chip LDO regulator. |
| 41 | AGND | power_in | 0V analog ground input. |
| 42 | TEST | input | IC test pin that must be connected to GND for normal operation. |
| 43 | EEDATA | bidirectional | EEPROM data I/O that connects directly to EEPROM data-in and to data-out through 2.2 kΩ, with data-out pulled to VCCD through 10 kΩ; it is tri-stated during reset. |
| 44 | EECLK | output | Clock output to the EEPROM that is tri-stated during device reset. |
| 45 | EECS | bidirectional | EEPROM chip select that is tri-stated during device reset. |
| 46 | VCCIO | power_in | +3.3V I/O interface power supply input. |
| 47 | GND | power_in | 0V ground input. |
| 48 | GND | power_in | 0V ground input. |
| 49 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |
Key specifications
| Parameter | Value |
|---|---|
| Manufacturer | FTDI |
| Package | QFN-48-EP(8x8) |
| Category | Interface ICs |
| Pins | 49 |
Electrical characteristics
Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).
| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage Temperature | -65 | 150 | Degrees C | 48 | |||
| Ambient Operating Temperature (Power Applied) | -40 | 85 | Degrees C | 48 | |||
| VCORE Supply Voltage | VCORE | -0.3 | 2 | V | 48 | ||
| VCCIO IO Voltage | VCCIO | -0.3 | 4 | V | 48 | ||
| DC Input Voltage, USBDP and USBDM | -0.5 | 3.63 | V | 48 | |||
| DC Input Voltage, High Impedance Bi-directionals (ACBUS and ADBUS powered from VCCIO) | -0.3 | 5.8 | V | 48 | |||
| DC Output Current, Outputs | 16 | mA | 48 | ||||
| VCORE VCC Core Operating Supply Voltage | VCORE | 1.62 | 1.8 | 1.98 | V | 49 | |
| VCCIO Operating Supply Voltage | VCCIO | 2.97 | 3.63 | V | Cells are 5V tolerant | 49 | |
| VREGIN Voltage regulator Input (5 Volts) | VREGIN | 3.6 | 5 | 5.5 | V | 5 volt input to VREGIN | 49 |
| VREGIN Voltage regulator Input (3.3 Volts) | VREGIN | 3.3 | 3.3 | 3.6 | V | 3.3 volt input to VREGIN | 49 |
| Output Voltage High | Voh | 2.4 | V | Ioh = +/-2mA | 50 | ||
| Output Voltage Low | Vol | 0 | 0.4 | V | Iol = +/-2mA | 50 | |
| Input low Switching Threshold (LVTTL) | Vil | 0.8 | V | LVTTL | 50 | ||
| Input High Switching Threshold (LVTTL) | Vih | 2 | V | LVTTL | 50 | ||
| Schmitt trigger negative going threshold voltage | Vt- | 0.8 | 1.1 | V | 50 | ||
| Schmitt trigger positive going threshold voltage | Vt+ | 1.6 | 2 | V | 50 | ||
| Input pull-up resistance | Rpu | 40 | 75 | 190 | KΩ | Vin = 0 | 50 |
| Input pull-down resistance | Rpd | 40 | 75 | 190 | KΩ | Vin =VCCIO | 50 |
| Input Leakage Current | Iin | -10 | 10 | μA | Vin = 0 | 50 | |
| Tri-state output leakage current | Ioz | -10 | 10 | μA | Vin = 5.5V or 0 | 50 | |
| PHY Operating Supply Voltage | VPHY, VPLL | 3 | 3.3 | 3.6 | V | 3.3V I/O | 51 |
| PHY Operating Supply Current | Iccphy | 30 | 60 | mA | Hi-speed operation at 480 MHz | 51 | |
| PHY Operating Supply Current (USB Suspend) | Iccphy(susp) | 10 | 50 | μA | USB Suspend | 51 | |
| PHY Input low Switching Threshold | Vil | 0.8 | V | 51 | |||
| PHY Input High Switching Threshold | Vih | 2 | V | 51 | |||
| PHY Output Voltage Low | Vol | 0.2 | V | 51 | |||
| Human Body Model (HBM) | -2 | 2 | kV | JEDEC EIA/JESD22-A114-B, Class 2 | 51 | ||
| Machine Mode (MM) | -200 | 200 | V | JEDEC EIA/JESD22-A115-A, Class B | 51 | ||
| Charge Device Model (CDM) | -500 | 500 | V | JEDEC EIA/ JESD22-C101-D, Class-III | 51 | ||
| Latch-up | -200 | 200 | mA | JESD78, Trigger Class-II | 51 | ||
| OSCI Input Voltage | Vin | 2.97 | 3.3 | 3.63 | V | 55 | |
| Input Frequency tolerance (12 MHz) | Fin | -30 | 30 | ppm | ± 30ppm | 55 | |
| Cycle to cycle jitter | Ji | 150 | pS | 55 |
CAD (KiCad official)
- Symbol:
FT232HQ-REEL - Footprint:
Package_DFN_QFN:QFN-48-1EP_8x8mm_P0.5mm_EP6.2x6.2mm - 3D model: QFN-48-EP(8x8), generated from the KiCad footprint (body from the F.Fab outline, terminals on the pads, 0.9 mm nominal QFN height). Neither the vendor nor KiCad ships a 3D model for this package, so the dimensions are nominal, not the manufacturer's CAD (STEP)
- 3D model files:
ft232hq-reel-etched.step/ft232hq-reel-etched.glbcarry the MPN laser-etched on the die in a toggleableAdom.LaserEtchgroup (Fusion-ready);ft232hq-reel.step/ft232hq-reel.glbare the bare package body.
Provenance
Data extracted from the manufacturer datasheet, not a distributor listing:
- Datasheet: FTDI datasheet (66 pp, sha256
37614c3b44603005, retrieved 2026-10-23, tier: lcsc) - Extractor: parts-factory
2.0.0/extract_pins 0.3, primaryclaude-haiku-5-5(text), consensusclaude-sonnet-5-5(agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish. - CAD: KiCad official libraries (CC-BY-SA 4.0).