FTDI USB ICs, QFN-68(8x8). Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

Overview Files Discover Packages Releases Dependencies Issues Breadcrumbs Pull Requests Activity

main

Ray Publish 0.1.0 8f4fa6e 18h ago

FT2232HPQ-TRAY

FTDI · USB ICs · QFN-68(8x8)

FT2232HPQ-TRAY from FTDI, in a QFN-68(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	EECLK	output	Clock signal output to the EEPROM, tri-state during device reset.
2	EEDATA	bidirectional	EEPROM data I/O, connected directly to EEPROM Data-In and to Data-Out via a 2.2K resistor with Data-Out pulled to VCC via 10K; tri-state during reset.
3	TEST	input	IC test pin, connect to GND for normal operation.
4	RESET#	input	Active-low reset input; tie to VCCIO (+3.3V) if not used.
5	GPIO3	bidirectional	GPIO3 pin, default function is input with weak pull-down.
6	ADBUS0	bidirectional	Channel A I/O bit 0 (TXD in RS232, D0 in FIFO/bit-bang, TCK/SK in MPSSE, AD0 in host bus emulation).
7	ADBUS1	bidirectional	Channel A I/O bit 1 (RXD in RS232, D1 in FIFO/bit-bang, TDI/DO in MPSSE, AD1 in host bus emulation).
8	VCORE	power_in	+1.2V core supply input; connect to VREGOUT when using the internal regulator.
9	GND	power_in	Ground.
10	VCCIO	power_in	+3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
11	ADBUS2	bidirectional	Channel A I/O bit 2 (RTS# in RS232, D2 in FIFO/bit-bang, TDO/DI in MPSSE, AD2 in host bus emulation).
12	ADBUS3	bidirectional	Channel A I/O bit 3 (CTS# in RS232, D3 in FIFO/bit-bang, TMS/CS in MPSSE, AD3 in host bus emulation).
13	ADBUS4	bidirectional	Channel A I/O bit 4 (DTR# in RS232, D4 in FIFO/bit-bang, GPIOL0 in MPSSE, AD4 in host bus emulation).
14	ADBUS5	bidirectional	Channel A I/O bit 5 (DSR# in RS232, D5 in FIFO/bit-bang, GPIOL1 in MPSSE, AD5 in host bus emulation).
15	ADBUS6	bidirectional	Channel A I/O bit 6 (DCD# in RS232, D6 in FIFO/bit-bang, GPIOL2 in MPSSE, AD6 in host bus emulation).
16	ADBUS7	bidirectional	Channel A I/O bit 7 (RI# in RS232, D7 in FIFO/bit-bang, GPIOL3 in MPSSE, AD7 in host bus emulation).
17	ACBUS0	bidirectional	Channel A control bit 0 (TXDEN in RS232, RXF# in FIFO, GPIOH0 in MPSSE, CS# in CPU-style FIFO, A8 in host bus emulation).
18	ACBUS1	bidirectional	Channel A control bit 1 (TXE# in FIFO, WRSTB# in bit-bang, GPIOH1 in MPSSE, A0 in CPU-style FIFO, A9 in host bus emulation).
19	ACBUS2	bidirectional	Channel A control bit 2 (RD# in FIFO, RDSTB# in bit-bang, GPIOH2 in MPSSE, A10 in host bus emulation).
20	ACBUS3	bidirectional	Channel A control bit 3 (RXLED# in RS232, WR# in FIFO, GPIOH3 in MPSSE, A11 in host bus emulation).
21	ACBUS4	bidirectional	Channel A control bit 4 (TXLED# in RS232, SIWUA in FIFO/bit-bang, GPIOH4 in MPSSE, A12 in host bus emulation); tie SIWU to VCCIO if unused.
22	ACBUS5	bidirectional	Channel A control bit 5 (CLKOUT in synchronous FIFO, GPIOH5 in MPSSE, A13 in host bus emulation).
23	ACBUS6	bidirectional	Channel A control bit 6 (OE# in synchronous FIFO, GPIOH6 in MPSSE, A14 in host bus emulation).
24	ACBUS7	bidirectional	Channel A control bit 7 (GPIOH7 in MPSSE, A15 in host bus emulation).
25	VCORE	power_in	+1.2V core supply input; connect to VREGOUT when using the internal regulator.
26	VCCIO	power_in	+3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
27	OSCI	input	Oscillator input (12 MHz crystal).
28	OSCO	output	Oscillator output (12 MHz crystal).
29	GND	power_in	Ground.
30	VREGIN	power_in	+3.3V input to the integrated 1.2V voltage regulator.
31	VREGOUT	power_out	+1.2V regulator output; connect to VCORE with a 3.3uF filter capacitor and do not use to power other circuits.
32	FSOURCE	power_in	FSOURCE input pin for EFUSE; leave floating for normal operation.
33	VPP	power_in	VPP input pin for EFUSE; leave floating for normal operation.
34	BDBUS0	bidirectional	Channel B I/O bit 0 (TXD in RS232, D0 in FIFO/bit-bang, TCK/SK in MPSSE, FSDI in fast serial, CS# in host bus emulation).
35	BDBUS1	bidirectional	Channel B I/O bit 1 (RXD in RS232, D1 in FIFO/bit-bang, TDI/DO in MPSSE, FSCLK in fast serial, ALE in host bus emulation).
36	BDBUS2	bidirectional	Channel B I/O bit 2 (RTS# in RS232, D2 in FIFO/bit-bang, TDO/DI in MPSSE, FSDO in fast serial, RD# in host bus emulation).
37	BDBUS3	bidirectional	Channel B I/O bit 3 (CTS# in RS232, D3 in FIFO/bit-bang, TMS/CS in MPSSE, FSCTS in fast serial, WR# in host bus emulation).
38	BDBUS4	bidirectional	Channel B I/O bit 4 (DTR# in RS232, D4 in FIFO/bit-bang, GPIOL0 in MPSSE, IORDY in host bus emulation).
39	VCCIO	power_in	+3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
40	BDBUS5	bidirectional	Channel B I/O bit 5 (DSR# in RS232, D5 in FIFO/bit-bang, GPIOL1 in MPSSE, CLKOUT in host bus emulation).
41	BDBUS6	bidirectional	Channel B I/O bit 6 (DCD# in RS232, D6 in FIFO/bit-bang, GPIOL2 in MPSSE, I/O0 in host bus emulation).
42	BDBUS7	bidirectional	Channel B I/O bit 7 (RI# in RS232, D7 in FIFO/bit-bang, GPIOL3 in MPSSE, I/O1 in host bus emulation).
43	SUSPEND#	output	Active-low output asserted when USB is in suspend mode.
44	VCORE	power_in	+1.2V core supply input; connect to VREGOUT when using the internal regulator.
45	BCBUS0	bidirectional	Channel B control bit 0 (TXDEN in RS232, RXF# in FIFO, GPIOH0 in MPSSE, CS# in CPU-style FIFO).
46	BCBUS1	bidirectional	Channel B control bit 1 (TXE# in FIFO, WRSTB# in bit-bang, GPIOH1 in MPSSE, A0 in CPU-style FIFO).
47	BCBUS2	bidirectional	Channel B control bit 2 (RD# in FIFO, RDSTB# in bit-bang, GPIOH2 in MPSSE).
48	BCBUS3	bidirectional	Channel B control bit 3 (RXLED# in RS232, WR# in FIFO, GPIOH3 in MPSSE).
49	BCBUS4	bidirectional	Channel B control bit 4 (TXLED# in RS232, SIWUB in FIFO/bit-bang, GPIOH4 in MPSSE); tie SIWU to VCCIO if unused.
50	BCBUS5	bidirectional	Channel B control bit 5 (GPIOH5 in MPSSE).
51	VCCIO	power_in	+3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails.
52	BCBUS6	bidirectional	Channel B control bit 6 (GPIOH6 in MPSSE).
53	BCBUS7	bidirectional	Channel B control bit 7 (PWRSAV# in most modes, GPIOH7 in MPSSE).
54	GPIO2	bidirectional	GPIO2 or I2C_INT# pin, default function is GPIO2 input with weak pull-down.
55	GPIO1	bidirectional	GPIO1 or I2C_SCL pin, default function is GPIO1 input with weak pull-down.
56	GPIO0	bidirectional	GPIO0 or I2C_SDA pin, default function is GPIO0 input with weak pull-down.
57	VCC_USB	power_in	+3.3V input for the internal USB PHY; must come from a +3.3V regulator (not directly from USB supply), LC filtering recommended.
58	DM	bidirectional	USB data signal minus.
59	DP	bidirectional	USB data signal plus.
60	REF	input	Current reference input; connect via a 12K Ohm 1% resistor to GND.
61	VCC_PD	power_in	+3.3V input for the internal PD PHY.
62	PD1_CC2	bidirectional	Analog I/O pin for PD1 CC2.
63	PD1_SVBUS	input	Analog input for scaled-down VBUS sensing for PD1; VBUS must be divided by 10 before this pin.
64	PD1_VCONN	power_in	Power input for the PD1 VCONN power source; connect to 3.3V.
65	PD1_CC1	bidirectional	Analog I/O pin for PD1 CC1.
66	VCORE	power_in	+1.2V core supply input; connect to VREGOUT when using the internal regulator.
67	PWREN#	output	Active-low power-enable output: 0 = normal operation, 1 = USB suspend or device not configured.
68	EECS	bidirectional	EEPROM chip select, tri-state during device reset.
69	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	FTDI
Package	QFN-68(8x8)
Category	Communication Interface Chip/UART/485/232
Pins	69

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
VCORE Operating Supply Voltage	VCORE	1.08	1.2	1.32	V		41
VCCIO Operating Supply Voltage	VCCIO	2.97	3.3	3.63	V	Cells are 5V tolerant	41
VREGIN Voltage regulator input	VREGIN	3	3.3	3.6	V		41
VREGOUT Voltage regulator output	VREGOUT	1.08	1.2	1.32	V		41
Input low switching threshold	Vil			0.8	V	LVTTL	42
Input high switching threshold	Vih	2			V	LVTTL	42
Schmitt trigger negative going threshold voltage	Vt-	0.8	1.1		V		42
Schmitt trigger positive going threshold voltage	Vt+		1.6	2	V		42
Input pull-up resistance	Rpu	40	75	190	KΩ	Vin = 0	42
Input pull-down resistance	Rpd	40	75	190	KΩ	Vin =VCCIO	42
Input leakage current	Iin	15	45	85	μA	Vin = 0	42
Tri-state output leakage current	Ioz	-10		10	μA	Vin = 5.5V or 0	42
Junction temperature	TJ	-40	25	125	°C	FT2233HP/FT2232HP	43
Storage temperature		-65		150	°C		41
Ambient operating temperature		-40		85	°C	Power applied	41
VCORE supply voltage	VCORE	-0.3		2	V		41
VCCIO IO voltage	VCCIO	-0.3		4	V		41
DC input voltage USBDP and USBDM		-0.5		3.63	V		41
DC input voltage high impedance bi-directional		-0.3		5.8	V	powered from VCCIO	41
DC input voltage all other inputs		-0.5			V	upper limit VCCIO + 0.5 V	41
DC output current outputs				16	mA		41
Regulator current	Ireg		22.37	150	mA	VREGIN +3.3V and data transfer with 12Mbps	41
VREGIN suspend supply current	Icc1s		132.2		µA	USB Suspend	41
VCC_USB operating supply current	I_vcc_usb		22.36		mA	Data transfer with 12Mbps	41
VCC_IO operating supply current	I_vccio		1.72		mA	Data transfer with 12Mbps	41
VCC_PD suspend supply current	I_vcc_pd		23.5		uA	PD suspend	41
Output voltage high	Voh	2.4	3.14		V	Ioh = +/-2mA, I/O Drive strength = 4mA	42
Output voltage low	Vol		0.18	0.4	V	Iol = +/-2mA, I/O Drive strength = 4mA	42
Thermal resistance junction-ambient (FT2232HPQ)	ѲJA		23.65		°C/W	Preliminary data	43
Thermal resistance junction-case (FT2232HPQ)	ѲJC		9.35		°C/W	Preliminary data	43

CAD (KiCad official)

Symbol: FT2232HPQ-TRAY
Footprint: Package_DFN_QFN:QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm
3D model: QFN-68(8x8) (KiCad packages3D, STEP)
3D model files: ft2232hpq-tray-etched.step / ft2232hpq-tray-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); ft2232hpq-tray.step / ft2232hpq-tray.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: FTDI datasheet (51 pp, sha256 d8534b366fa17f2d, retrieved 2026-10-31, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-sonnet-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF

# FT2232HPQ-TRAY

**FTDI** · USB ICs · QFN-68(8x8)

FT2232HPQ-TRAY from FTDI, in a QFN-68(8x8). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | EECLK | output | Clock signal output to the EEPROM, tri-state during device reset. |
| 2 | EEDATA | bidirectional | EEPROM data I/O, connected directly to EEPROM Data-In and to Data-Out via a 2.2K resistor with Data-Out pulled to VCC via 10K; tri-state during reset. |
| 3 | TEST | input | IC test pin, connect to GND for normal operation. |
| 4 | RESET# | input | Active-low reset input; tie to VCCIO (+3.3V) if not used. |
| 5 | GPIO3 | bidirectional | GPIO3 pin, default function is input with weak pull-down. |
| 6 | ADBUS0 | bidirectional | Channel A I/O bit 0 (TXD in RS232, D0 in FIFO/bit-bang, TCK/SK in MPSSE, AD0 in host bus emulation). |
| 7 | ADBUS1 | bidirectional | Channel A I/O bit 1 (RXD in RS232, D1 in FIFO/bit-bang, TDI/DO in MPSSE, AD1 in host bus emulation). |
| 8 | VCORE | power_in | +1.2V core supply input; connect to VREGOUT when using the internal regulator. |
| 9 | GND | power_in | Ground. |
| 10 | VCCIO | power_in | +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails. |
| 11 | ADBUS2 | bidirectional | Channel A I/O bit 2 (RTS# in RS232, D2 in FIFO/bit-bang, TDO/DI in MPSSE, AD2 in host bus emulation). |
| 12 | ADBUS3 | bidirectional | Channel A I/O bit 3 (CTS# in RS232, D3 in FIFO/bit-bang, TMS/CS in MPSSE, AD3 in host bus emulation). |
| 13 | ADBUS4 | bidirectional | Channel A I/O bit 4 (DTR# in RS232, D4 in FIFO/bit-bang, GPIOL0 in MPSSE, AD4 in host bus emulation). |
| 14 | ADBUS5 | bidirectional | Channel A I/O bit 5 (DSR# in RS232, D5 in FIFO/bit-bang, GPIOL1 in MPSSE, AD5 in host bus emulation). |
| 15 | ADBUS6 | bidirectional | Channel A I/O bit 6 (DCD# in RS232, D6 in FIFO/bit-bang, GPIOL2 in MPSSE, AD6 in host bus emulation). |
| 16 | ADBUS7 | bidirectional | Channel A I/O bit 7 (RI# in RS232, D7 in FIFO/bit-bang, GPIOL3 in MPSSE, AD7 in host bus emulation). |
| 17 | ACBUS0 | bidirectional | Channel A control bit 0 (TXDEN in RS232, RXF# in FIFO, GPIOH0 in MPSSE, CS# in CPU-style FIFO, A8 in host bus emulation). |
| 18 | ACBUS1 | bidirectional | Channel A control bit 1 (TXE# in FIFO, WRSTB# in bit-bang, GPIOH1 in MPSSE, A0 in CPU-style FIFO, A9 in host bus emulation). |
| 19 | ACBUS2 | bidirectional | Channel A control bit 2 (RD# in FIFO, RDSTB# in bit-bang, GPIOH2 in MPSSE, A10 in host bus emulation). |
| 20 | ACBUS3 | bidirectional | Channel A control bit 3 (RXLED# in RS232, WR# in FIFO, GPIOH3 in MPSSE, A11 in host bus emulation). |
| 21 | ACBUS4 | bidirectional | Channel A control bit 4 (TXLED# in RS232, SIWUA in FIFO/bit-bang, GPIOH4 in MPSSE, A12 in host bus emulation); tie SIWU to VCCIO if unused. |
| 22 | ACBUS5 | bidirectional | Channel A control bit 5 (CLKOUT in synchronous FIFO, GPIOH5 in MPSSE, A13 in host bus emulation). |
| 23 | ACBUS6 | bidirectional | Channel A control bit 6 (OE# in synchronous FIFO, GPIOH6 in MPSSE, A14 in host bus emulation). |
| 24 | ACBUS7 | bidirectional | Channel A control bit 7 (GPIOH7 in MPSSE, A15 in host bus emulation). |
| 25 | VCORE | power_in | +1.2V core supply input; connect to VREGOUT when using the internal regulator. |
| 26 | VCCIO | power_in | +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails. |
| 27 | OSCI | input | Oscillator input (12 MHz crystal). |
| 28 | OSCO | output | Oscillator output (12 MHz crystal). |
| 29 | GND | power_in | Ground. |
| 30 | VREGIN | power_in | +3.3V input to the integrated 1.2V voltage regulator. |
| 31 | VREGOUT | power_out | +1.2V regulator output; connect to VCORE with a 3.3uF filter capacitor and do not use to power other circuits. |
| 32 | FSOURCE | power_in | FSOURCE input pin for EFUSE; leave floating for normal operation. |
| 33 | VPP | power_in | VPP input pin for EFUSE; leave floating for normal operation. |
| 34 | BDBUS0 | bidirectional | Channel B I/O bit 0 (TXD in RS232, D0 in FIFO/bit-bang, TCK/SK in MPSSE, FSDI in fast serial, CS# in host bus emulation). |
| 35 | BDBUS1 | bidirectional | Channel B I/O bit 1 (RXD in RS232, D1 in FIFO/bit-bang, TDI/DO in MPSSE, FSCLK in fast serial, ALE in host bus emulation). |
| 36 | BDBUS2 | bidirectional | Channel B I/O bit 2 (RTS# in RS232, D2 in FIFO/bit-bang, TDO/DI in MPSSE, FSDO in fast serial, RD# in host bus emulation). |
| 37 | BDBUS3 | bidirectional | Channel B I/O bit 3 (CTS# in RS232, D3 in FIFO/bit-bang, TMS/CS in MPSSE, FSCTS in fast serial, WR# in host bus emulation). |
| 38 | BDBUS4 | bidirectional | Channel B I/O bit 4 (DTR# in RS232, D4 in FIFO/bit-bang, GPIOL0 in MPSSE, IORDY in host bus emulation). |
| 39 | VCCIO | power_in | +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails. |
| 40 | BDBUS5 | bidirectional | Channel B I/O bit 5 (DSR# in RS232, D5 in FIFO/bit-bang, GPIOL1 in MPSSE, CLKOUT in host bus emulation). |
| 41 | BDBUS6 | bidirectional | Channel B I/O bit 6 (DCD# in RS232, D6 in FIFO/bit-bang, GPIOL2 in MPSSE, I/O0 in host bus emulation). |
| 42 | BDBUS7 | bidirectional | Channel B I/O bit 7 (RI# in RS232, D7 in FIFO/bit-bang, GPIOL3 in MPSSE, I/O1 in host bus emulation). |
| 43 | SUSPEND# | output | Active-low output asserted when USB is in suspend mode. |
| 44 | VCORE | power_in | +1.2V core supply input; connect to VREGOUT when using the internal regulator. |
| 45 | BCBUS0 | bidirectional | Channel B control bit 0 (TXDEN in RS232, RXF# in FIFO, GPIOH0 in MPSSE, CS# in CPU-style FIFO). |
| 46 | BCBUS1 | bidirectional | Channel B control bit 1 (TXE# in FIFO, WRSTB# in bit-bang, GPIOH1 in MPSSE, A0 in CPU-style FIFO). |
| 47 | BCBUS2 | bidirectional | Channel B control bit 2 (RD# in FIFO, RDSTB# in bit-bang, GPIOH2 in MPSSE). |
| 48 | BCBUS3 | bidirectional | Channel B control bit 3 (RXLED# in RS232, WR# in FIFO, GPIOH3 in MPSSE). |
| 49 | BCBUS4 | bidirectional | Channel B control bit 4 (TXLED# in RS232, SIWUB in FIFO/bit-bang, GPIOH4 in MPSSE); tie SIWU to VCCIO if unused. |
| 50 | BCBUS5 | bidirectional | Channel B control bit 5 (GPIOH5 in MPSSE). |
| 51 | VCCIO | power_in | +3.3V I/O interface power supply input; all VCCIO pins must be connected or the device fails. |
| 52 | BCBUS6 | bidirectional | Channel B control bit 6 (GPIOH6 in MPSSE). |
| 53 | BCBUS7 | bidirectional | Channel B control bit 7 (PWRSAV# in most modes, GPIOH7 in MPSSE). |
| 54 | GPIO2 | bidirectional | GPIO2 or I2C_INT# pin, default function is GPIO2 input with weak pull-down. |
| 55 | GPIO1 | bidirectional | GPIO1 or I2C_SCL pin, default function is GPIO1 input with weak pull-down. |
| 56 | GPIO0 | bidirectional | GPIO0 or I2C_SDA pin, default function is GPIO0 input with weak pull-down. |
| 57 | VCC_USB | power_in | +3.3V input for the internal USB PHY; must come from a +3.3V regulator (not directly from USB supply), LC filtering recommended. |
| 58 | DM | bidirectional | USB data signal minus. |
| 59 | DP | bidirectional | USB data signal plus. |
| 60 | REF | input | Current reference input; connect via a 12K Ohm 1% resistor to GND. |
| 61 | VCC_PD | power_in | +3.3V input for the internal PD PHY. |
| 62 | PD1_CC2 | bidirectional | Analog I/O pin for PD1 CC2. |
| 63 | PD1_SVBUS | input | Analog input for scaled-down VBUS sensing for PD1; VBUS must be divided by 10 before this pin. |
| 64 | PD1_VCONN | power_in | Power input for the PD1 VCONN power source; connect to 3.3V. |
| 65 | PD1_CC1 | bidirectional | Analog I/O pin for PD1 CC1. |
| 66 | VCORE | power_in | +1.2V core supply input; connect to VREGOUT when using the internal regulator. |
| 67 | PWREN# | output | Active-low power-enable output: 0 = normal operation, 1 = USB suspend or device not configured. |
| 68 | EECS | bidirectional | EEPROM chip select, tri-state during device reset. |
| 69 | EP | passive | Exposed pad (from the footprint; not named in the datasheet pin table). |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | FTDI |
| Package | QFN-68(8x8) |
| Category | Communication Interface Chip/UART/485/232 |
| Pins | 69 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| VCORE Operating Supply Voltage | VCORE | 1.08 | 1.2 | 1.32 | V |  | 41 |
| VCCIO Operating Supply Voltage | VCCIO | 2.97 | 3.3 | 3.63 | V | Cells are 5V tolerant | 41 |
| VREGIN Voltage regulator input | VREGIN | 3 | 3.3 | 3.6 | V |  | 41 |
| VREGOUT Voltage regulator output | VREGOUT | 1.08 | 1.2 | 1.32 | V |  | 41 |
| Input low switching threshold | Vil |  |  | 0.8 | V | LVTTL | 42 |
| Input high switching threshold | Vih | 2 |  |  | V | LVTTL | 42 |
| Schmitt trigger negative going threshold voltage | Vt- | 0.8 | 1.1 |  | V |  | 42 |
| Schmitt trigger positive going threshold voltage | Vt+ |  | 1.6 | 2 | V |  | 42 |
| Input pull-up resistance | Rpu | 40 | 75 | 190 | KΩ | Vin = 0 | 42 |
| Input pull-down resistance | Rpd | 40 | 75 | 190 | KΩ | Vin =VCCIO | 42 |
| Input leakage current | Iin | 15 | 45 | 85 | μA | Vin = 0 | 42 |
| Tri-state output leakage current | Ioz | -10 |  | 10 | μA | Vin = 5.5V or 0 | 42 |
| Junction temperature | TJ | -40 | 25 | 125 | °C | FT2233HP/FT2232HP | 43 |
| Storage temperature |  | -65 |  | 150 | °C |  | 41 |
| Ambient operating temperature |  | -40 |  | 85 | °C | Power applied | 41 |
| VCORE supply voltage | VCORE | -0.3 |  | 2 | V |  | 41 |
| VCCIO IO voltage | VCCIO | -0.3 |  | 4 | V |  | 41 |
| DC input voltage USBDP and USBDM |  | -0.5 |  | 3.63 | V |  | 41 |
| DC input voltage high impedance bi-directional |  | -0.3 |  | 5.8 | V | powered from VCCIO | 41 |
| DC input voltage all other inputs |  | -0.5 |  |  | V | upper limit VCCIO + 0.5 V | 41 |
| DC output current outputs |  |  |  | 16 | mA |  | 41 |
| Regulator current | Ireg |  | 22.37 | 150 | mA | VREGIN +3.3V and data transfer with 12Mbps | 41 |
| VREGIN suspend supply current | Icc1s |  | 132.2 |  | µA | USB Suspend | 41 |
| VCC_USB operating supply current | I_vcc_usb |  | 22.36 |  | mA | Data transfer with 12Mbps | 41 |
| VCC_IO operating supply current | I_vccio |  | 1.72 |  | mA | Data transfer with 12Mbps | 41 |
| VCC_PD suspend supply current | I_vcc_pd |  | 23.5 |  | uA | PD suspend | 41 |
| Output voltage high | Voh | 2.4 | 3.14 |  | V | Ioh = +/-2mA, I/O Drive strength = 4mA | 42 |
| Output voltage low | Vol |  | 0.18 | 0.4 | V | Iol = +/-2mA, I/O Drive strength = 4mA | 42 |
| Thermal resistance junction-ambient (FT2232HPQ) | ѲJA |  | 23.65 |  | °C/W | Preliminary data | 43 |
| Thermal resistance junction-case (FT2232HPQ) | ѲJC |  | 9.35 |  | °C/W | Preliminary data | 43 |

## CAD (KiCad official)

- Symbol: `FT2232HPQ-TRAY`
- Footprint: `Package_DFN_QFN:QFN-68-1EP_8x8mm_P0.4mm_EP5.2x5.2mm`
- 3D model: QFN-68(8x8) (KiCad packages3D, STEP)
- 3D model files: `ft2232hpq-tray-etched.step` / `ft2232hpq-tray-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `ft2232hpq-tray.step` / `ft2232hpq-tray.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [FTDI datasheet](docs/ft2232hpq-tray-datasheet.pdf) (51 pp, sha256 `d8534b366fa17f2d`, retrieved 2026-10-31, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-sonnet-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/ft2232hpq-tray-datasheet.pdf)

FT2232HPQ-TRAY

Verified FT2232HPQ-TRAY

Verification log 1 record

FT2232HPQ-TRAY

Pinout

Key specifications

Electrical characteristics

CAD (KiCad official)

Provenance