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Contents

Pinout
Key specifications
Electrical characteristics
CAD (KiCad official)
Provenance

README

markdown

FSV9523

Forsinve · RFID ICs · QFN-32(5x5)

FSV9523 from Forsinve, in a QFN-32(5x5). Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin	Name	Type	Function
1	I2C	input	I2C-bus enable input; a logic 1 on this pin selects the I2C-bus interface during interface detection after reset (Table 5).
2	PVDD	power_in	Pin power supply, which must always be the same or a lower voltage than DVDD (VDD(PVDD) ≤ VDDD).
3	DVDD	power_in	Digital power supply, which must always be the same voltage as AVDD and TVDD.
4	DVSS	power_in	Digital ground; connection of the underside heatsink pad is not necessary, and an optional connection to this pin is possible.
5	PVSS	power_in	Pin power supply ground.
6	NRSTPD	input	Reset and power-down input: a positive edge enables reset, and a LOW level enables power-down, which switches off the internal current sinks, inhibits the oscillator and disconnects the input pins from the outside world.
7	MFIN	input	MIFARE signal input, powered from the SVDD supply (pin 9).
8	MFOUT	output	MIFARE signal output, powered from the SVDD supply (pin 9).
9	SVDD	power_in	MFIN and MFOUT pin power supply.
10	TVSS	power_in	Transmitter output stage 1 ground.
11	TX1	output	Transmitter 1 modulated 13.56 MHz energy carrier output, whose output stage is supplied from TVDD.
12	TVDD	power_in	Transmitter power supply for the output stages of transmitters 1 and 2, which must always be the same voltage as DVDD and AVDD.
13	TX2	output	Transmitter 2 modulated 13.56 MHz energy carrier output, whose output stage is supplied from TVDD.
14	TVSS	power_in	Transmitter output stage 2 ground.
15	AVDD	power_in	Analog power supply, which must always be the same voltage as DVDD and TVDD (VDDA = 3 V in the quick reference conditions).
16	VMID	power_in	Internal reference voltage pin (type P as printed in the datasheet).
17	RX	input	RF signal input for the receiver.
18	AVSS	power_in	Analog ground.
19	AUX1	output	Auxiliary output for test purposes.
20	AUX2	output	Auxiliary output for test purposes.
21	OSCIN	input	Crystal oscillator inverting amplifier input, which is also the input for an externally generated clock of fclk = 27.12 MHz.
22	OSCOUT	output	Crystal oscillator inverting amplifier output.
23	IRQ	output	Interrupt request output that indicates an interrupt event.
24	SDA/NSS/RX	bidirectional	I2C-bus serial data line input/output, which alternatively serves as SPI slave select input NSS or UART address input RX depending on the detected host interface (Table 5).
25	D1/ADR_5	bidirectional	Test port I/O pin D1, which alternatively serves as I2C-bus address 5 input ADR_5; when SPI is used only D1 to D4 can be used as test pins.
26	D2/ADR_4	bidirectional	Test port I/O pin D2, which alternatively serves as I2C-bus address 4 input ADR_4.
27	D3/ADR_3	bidirectional	Test port I/O pin D3, which alternatively serves as I2C-bus address 3 input ADR_3.
28	D4/ADR_2	bidirectional	Test port I/O pin D4, which alternatively serves as I2C-bus address 2 input ADR_2.
29	D5/ADR_1/SCK/DTRQ	bidirectional	Test port I/O pin D5, which alternatively serves as I2C-bus address 1 input ADR_1, SPI serial clock input SCK, or UART request-to-send output DTRQ.
30	D6/ADR_0/MOSI/MX	bidirectional	Test port I/O pin D6, which alternatively serves as I2C-bus address 0 input ADR_0, SPI master out slave in MOSI, or UART output MX.
31	D7/SCL/MISO/TX	bidirectional	Test port I/O pin D7, which alternatively serves as I2C-bus clock input/output SCL, SPI master in slave out MISO, or UART data output TX.
32	EA	input	External address input used to code the I2C-bus address.
33	EP	passive	Exposed pad (from the footprint; not named in the datasheet pin table).

Key specifications

Parameter	Value
Manufacturer	Forsinve
Package	QFN-32(5x5)
Category	RF And Wireless
Pins	33

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter	Symbol	Min	Typ	Max	Unit	Conditions	Page
analog supply voltage	VDDA	-0.5		4	V		73
digital supply voltage	VDDD	-0.5		4	V		73
PVDD supply voltage	VDD(PVDD)	-0.5		4	V		73
TVDD supply voltage	VDD(TVDD)	-0.5		4	V		73
SVDD supply voltage	VDD(SVDD)	-0.5		4	V		73
input voltage, all input pins except MFIN and RX	VI	-0.5			V	all input pins except MFIN and RX	73
input voltage, pin MFIN	VI	-0.5			V	pin MFIN	73
total power dissipation per package	Ptot			200	mW	per package; VDDD in shortcut mode	73
junction temperature	Tj			100	°C		73
electrostatic discharge voltage, HBM	VESD			2000	V	HBM; 1500 Ω, 100 pF; JESD22-A114-B	73
electrostatic discharge voltage, MM	VESD			200	V	MM; 0.75 µH, 200 pF; JESD22-A114-A	73
electrostatic discharge voltage, charged device model, on all pins	VESD			200	V	Charged device model; JESD22-C101-A; on all pins	73
analog supply voltage	VDDA	2.5	3.3	3.6	V	VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V	74
digital supply voltage	VDDD	2.5	3.3	3.6	V	VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V	74
TVDD supply voltage	VDD(TVDD)	2.5	3.3	3.6	V	VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V	74
PVDD supply voltage	VDD(PVDD)	1.6	1.8	3.6	V	VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V; must be same or lower than VDDD	74
SVDD supply voltage	VDD(SVDD)	1.6		3.6	V	VSSA = VSSD = VSS(PVSS) = VSS(TVSS) = 0 V	74
ambient temperature	Tamb	-25		85	°C	HVQFN32	74
thermal resistance from junction to ambient	Rth(j-a)		40		K/W	in still air with exposed pin soldered on a 4 layer JEDEC PCB; HVQFN32	74
input leakage current, pins EA, I2C and NRSTPD	ILI	-1		1	µA		74
input leakage current, pin MFIN	ILI	-1		1	µA		74
input leakage current, pin SDA	ILI	-1		1	µA		75
input leakage current, pin OSCIN	ILI	-1		1	µA		75
input voltage, pin RX	Vi	1			V		75
input leakage current, pins D1 to D7	ILI	-1		1	µA		75
IOH HIGH-level output current, pins D1 to D7	IOH			4	mA	VDD(PVDD) = 3 V	76
IOL LOW-level output current, pins D1 to D7	IOL			4	mA	VDD(PVDD) = 3 V	76
IOL LOW-level output current, pin MFOUT	IOL			4	mA	VDD(SVDD) = 3 V	76
IOH HIGH-level output current, pin MFOUT	IOH			4	mA	VDD(SVDD) = 3 V	76
IOL LOW-level output current, pin IRQ	IOL			4	mA	VDD(PVDD) = 3 V	76
IOH HIGH-level output current, pin IRQ	IOH			4	mA	VDD(PVDD) = 3 V	76
IOL LOW-level output current, pins AUX1 and AUX2	IOL			4	mA	VDDD = 3 V	76
IOH HIGH-level output current, pins AUX1 and AUX2	IOH			4	mA	VDDD = 3 V	76
LOW-level output voltage, pins TX1 and TX2	VOL			0.15	V	VDD(TVDD) = 3 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh	77
LOW-level output voltage, pins TX1 and TX2	VOL			0.4	V	VDD(TVDD) = 3 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh	77
LOW-level output voltage, pins TX1 and TX2	VOL			0.24	V	VDD(TVDD) = 2.5 V; IDD(TVDD) = 32 mA; CWGsP[5:0] = 0Fh	77
LOW-level output voltage, pins TX1 and TX2	VOL			0.64	V	VDD(TVDD) = 2.5 V; IDD(TVDD) = 80 mA; CWGsP[5:0] = 0Fh	77
power-down current, hard power-down	Ipd			5	µA	VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V; hard power-down; pin NRSTPD set LOW	77
power-down current, soft power-down	Ipd			10	µA	VDDA = VDDD = VDD(TVDD) = VDD(PVDD) = 3 V; soft power-down; RF level detector on	77
digital supply current	IDDD		6.5	9	mA	pin DVDD; VDDD = 3 V	77
analog supply current	IDDA		7	10	mA	pin AVDD; VDDA = 3 V; CommandReg register's bit RcvOff = 0	77
analog supply current, receiver switched off	IDDA		3	5	mA	pin AVDD; VDDA = 3 V; CommandReg register's bit RcvOff = 1	77
PVDD supply current	IDD(PVDD)			40	mA	pin PVDD	77
TVDD supply current, continuous wave	IDD(TVDD)		60	100	mA	pin TVDD; continuous wave	77
SVDD supply current	IDD(SVDD)			4	mA	pin SVDD	77
clock duty cycle	clk	40	50	60	%		77
jitter time RMS	tjit			10	ps		77
equivalent series resistance	ESR			100	Ω		78
crystal power dissipation	Pxtal	50		100	µW		78
pulse width LOW line SCK	tWL	50			ns		78
pulse width HIGH line SCK	tWH	50			ns		78
SCK HIGH to data input hold time	th(SCKH-D)	25			ns	SCK to changing MOSI	78
data input to SCK HIGH set-up time	tsu(D-SCKH)	25			ns	changing MOSI to SCK	78
SCK LOW to data output hold time	th(SCKL-Q)			25	ns	SCK to changing MISO	79
SCK LOW to NSS HIGH time	t(SCKL-NSSH)	0			ns		79
NSS HIGH time before communication	tNSSH	50			ns		79
SCL clock frequency	fSCL	0		400	kHz	Fast mode	79
SCL clock frequency	fSCL	0		3400	kHz	High-speed mode	79

CAD (KiCad official)

Symbol: FSV9523
Footprint: Package_DFN_QFN:QFN-32-1EP_5x5mm_P0.5mm_EP3.3x3.3mm
3D model: QFN-32(5x5) (KiCad packages3D, STEP)
3D model files: fsv9523-etched.step / fsv9523-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fsv9523.step / fsv9523.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

Datasheet: Forsinve datasheet (88 pp, sha256 6463f993b9537679, retrieved 2026-10-18, tier: lcsc)
Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF