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FST3125DR2G

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onsemi Signal Switches, Multiplexers, Decoders, SOIC-14. Pinout cross-checked by two models against the datasheet, KiCad symbol/footprint/3D.

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FST3125DR2G

onsemi · Signal Switches, Multiplexers, Decoders · SOIC-14

FST3125DR2G from onsemi, in a SOIC-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

Pinout

Pin Name Type Function
1 OE1 input Active-low bus switch enable for switch 1; A1 connects to B1 when low and the switch is high-Z when high, TTL/CMOS compatible and must not be left open.
2 1A bidirectional Bus A port of switch 1, connected to 1B when OE1 is low.
3 1B bidirectional Bus B port of switch 1, connected to 1A when OE1 is low.
4 OE2 input Active-low bus switch enable for switch 2; A connects to B when low and the switch is high-Z when high, must not be left open.
5 2A bidirectional Bus A port of switch 2, connected to 2B when OE2 is low.
6 2B bidirectional Bus B port of switch 2, connected to 2A when OE2 is low.
7 GND power_in Ground pin.
8 3B bidirectional Bus B port of switch 3, connected to 3A when OE3 is low.
9 3A bidirectional Bus A port of switch 3, connected to 3B when OE3 is low.
10 OE3 input Active-low bus switch enable for switch 3; A connects to B when low and the switch is high-Z when high, must not be left open.
11 4B bidirectional Bus B port of switch 4, connected to 4A when OE4 is low.
12 4A bidirectional Bus A port of switch 4, connected to 4B when OE4 is low.
13 OE4 input Active-low bus switch enable for switch 4; A connects to B when low and the switch is high-Z when high, must not be left open.
14 VCC power_in Positive supply voltage, 4.0 V to 5.5 V recommended operating range (absolute maximum 7.0 V).

Key specifications

Parameter Value
Manufacturer onsemi
Package SOIC-14
Category Logic
Pins 14

Electrical characteristics

Limits as printed in the datasheet (page.json metadata.characteristics carries them as data).

Parameter Symbol Min Typ Max Unit Conditions Page
Supply Voltage Operating, Data Retention Only VCC 4 5.5 V Operating, Data Retention Only 3
Input Voltage VI 0 5.5 V Note 5 3
Output Voltage (HIGH or LOW State) VO 0 5.5 V HIGH or LOW state 3
Operating Free-Air Temperature TA -55 125 C 3
Input Transition Rise or Fall Rate t/V 0 5 ns/V Switch Control Input 3
Input Transition Rise or Fall Rate t/V 0 ns/V Switch I/O; max printed as DC 3
DC Supply Voltage VCC -0.5 7 V 3
DC Input Voltage VI -0.5 7 V 3
DC Output Voltage VO -0.5 7 V 3
DC Input Diode Current IIK 50 mA VI < GND 3
DC Output Diode Current IOK 50 mA VO < GND 3
DC Output Sink Current IO 128 mA 3
DC Supply Current per Supply Pin ICC 100 mA per supply pin 3
DC Ground Current per Ground Pin IGND 100 mA per ground pin 3
Storage Temperature Range TSTG -65 150 C 3
Lead Temperature TL 260 C 1 mm from case for 10 seconds 3
Junction Temperature Under Bias TJ 150 C Under bias 3
Thermal Resistance, junction to ambient JA 125 C/W SOIC; Note 1 (minimum pad spacing, FR4 board) 3
ESD Withstand Voltage Human Body Model VESD 4000 V Human Body Model (Note 2) 3
ESD Withstand Voltage Machine Model VESD 400 V Machine Model (Note 3) 3
ESD Withstand Voltage Charged Device Model VESD 2000 V Charged Device Model 3
Latchup Performance ILatchup 100 mA Above VCC and below GND at 85C (Note 4) 3
High-Level Input Voltage VIH 2 V VCC 4.0 to 5.5 V 4
Low-Level Input Voltage VIL 0.8 V VCC 4.0 to 5.5 V 4
Switch On Resistance RON 4 7 ohm VIN = 0 V, IIN = 64 mA, VCC 4.5 V 4
Switch On Resistance RON 8 15 ohm VIN = 2.4 V, IIN = 15 mA, VCC 4.5 V 4
Switch On Resistance RON 11 20 ohm VIN = 2.4 V, IIN = 15 mA, VCC 4.0 V 4
Prop Delay Bus to Bus tPHL, tPLH 0.25 ns VI = OPEN; Figures 3 and 4; VCC 4.5 to 5.5 V 4
Output Enable Time tPZH, tPZL 1 5 ns VI = 7 V for tPZL, VI = OPEN for tPZH; Figures 3 and 5; VCC 4.5 to 5.5 V 4
Output Enable Time tPZH, tPZL 5.5 ns VI = 7 V for tPZL, VI = OPEN for tPZH; Figures 3 and 5; VCC 4.0 V 4
Output Disable Time tPHZ, tPLZ 1.5 5.3 ns VI = 7 V for tPLZ, VI = OPEN for tPHZ; Figures 3 and 5; VCC 4.5 to 5.5 V 4
Output Disable Time tPHZ, tPLZ 5.6 ns VI = 7 V for tPLZ, VI = OPEN for tPHZ; Figures 3 and 5; VCC 4.0 V 4

CAD (KiCad official)

  • Symbol: FST3125DR2G
  • Footprint: Package_SO:SOIC-14_3.9x8.7mm_P1.27mm
  • 3D model: SOIC-14 (KiCad packages3D, STEP)
  • 3D model files: fst3125dr2g-etched.step / fst3125dr2g-etched.glb carry the MPN laser-etched on the die in a toggleable Adom.LaserEtch group (Fusion-ready); fst3125dr2g.step / fst3125dr2g.glb are the bare package body.

Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

  • Datasheet: onsemi datasheet (9 pp, sha256 dd073cc476dbf01e, retrieved 2026-10-18, tier: lcsc)
  • Extractor: parts-factory 2.0.0 / extract_pins 0.3, primary claude-haiku-5-5 (text), consensus claude-sonnet-5-5 (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
  • CAD: KiCad official libraries (CC-BY-SA 4.0).

Datasheet PDF