# FRTC8900S

**Nyfea** · Real Time Clocks · SOP-14

FRTC8900S from Nyfea, in a SOP-14. Pinout and pin descriptions extracted from the manufacturer datasheet (extract_pins, cross-checked by a second model); symbol, footprint, and 3D from KiCad-official CAD.

## Pinout

| Pin | Name | Type | Function |
|---|---|---|---|
| 1 | T1 | input | Manufacturer test pin; the datasheet says not to connect it externally. |
| 2 | SCL | input | Serial clock input for I2C bus communications. |
| 3 | FOUT | output | C-MOS 32.768 kHz output controlled by FOE; it outputs 32.768 kHz when FOE is high (depending on the FSEL bit) and goes high-impedance (Hi-Z) when output is stopped. |
| 4 | N.C. | unconnected | Not connected to the internal IC; leave open or connect to GND or VDD. |
| 5 | VBAT | power_in | Backup battery supply, 1.6 V to 5.5 V (3.0 V typ.); connect to VDD if battery switchover is not needed, or to a large-capacity capacitor or secondary battery otherwise. |
| 6 | VDD | power_in | Positive supply for normal operation, 2.5 V to 5.5 V (3.0 V typ.). |
| 7 | FOE | input | Input that controls FOUT output mode: FOUT is enabled when FOE is high and output stops when FOE is low. |
| 8 | N.C. | unconnected | Not connected to the internal IC; leave open or connect to GND or VDD. |
| 9 | N.C. | unconnected | Not connected to the internal IC; leave open or connect to GND or VDD. |
| 10 | /INT | output | Open-drain output that goes low to signal alarm, fixed-cycle timer, or time update interrupts; it is active only when the matching interrupt enable bit is set. |
| 11 | GND | power_in | Ground connection. |
| 12 | T2 | input | Manufacturer test pin; the datasheet says not to connect it externally. |
| 13 | SDA | bidirectional | I2C serial data line (N-channel open drain during output) that needs a pull-up resistor suited to the signal-line capacitance. |
| 14 | N.C. | unconnected | Not connected to the internal IC; leave open or connect to GND or VDD. |

## Key specifications

| Parameter | Value |
|---|---|
| Manufacturer | Nyfea |
| Package | SOP-14 |
| Category | Clock/Timing |
| Pins | 14 |

## Electrical characteristics

Limits as printed in the datasheet (page.json `metadata.characteristics` carries them as data).

| Parameter | Symbol | Min | Typ | Max | Unit | Conditions | Page |
|---|---|---|---|---|---|---|---|
| Storage temperature | Tstore | -55 |  | 125 | °C |  | 4 |
| DC supply voltage | VDD | -0.3 |  | 6.5 | V |  | 4 |
| Battery supply voltage | VBAT | -0.3 |  | 6.5 | V |  | 4 |
| Input voltage on FOE, SCL, SDA | VI | -0.3 |  | 6.5 | V | min printed GND-0.3 (GND = 0 V) | 4 |
| Output voltage on FOUT pins | VO1 | -0.3 |  |  | V | min printed GND-0.3 (GND = 0 V); max printed VDD+0.3, no numeric value | 4 |
| Output voltage on SDA and /INT pins | VO2 | -0.3 |  | 6.5 | V | min printed GND-0.3 (GND = 0 V) | 4 |
| Latch-up | LU | -200 |  | 200 | mA | printed ±200 | 4 |
| Charged Device Model | CDM |  |  | 1000 | V |  | 4 |
| Human Body Model | HBM |  |  | 4000 | V |  | 4 |
| Operating supply voltage in normal mode | VDD | 2.5 | 3 | 5.5 | V | normal mode | 4 |
| Backup power supply voltage | VBAT | 1.6 | 3 | 5.5 | V |  | 4 |
| Temp. compensation voltage | VTEM | 2 | 3 | 5.5 | V |  | 4 |
| Operating temperature | TOPR | -40 |  | 85 | °C |  | 4 |
| Average current consumption (1) | IDD1 |  | 0.59 | 2.4 | µA | VDD = 5 V; fSCL = 0 Hz, /INT = VDD, FOE = GND, VDD = VBAT, FOUT OFF (Hi-Z) | 5 |
| Average current consumption (2) | IDD2 |  | 0.54 | 2.2 | µA | VDD = 3 V; fSCL = 0 Hz, /INT = VDD, FOE = GND, VDD = VBAT, FOUT OFF (Hi-Z) | 5 |
| Average current consumption (3) | IDD3 |  | 1.66 | 3.4 | µA | VDD = 5 V; fSCL = 0 Hz, /INT = VDD, FOE = VDD, FOUT 32.768 kHz, CL = 0 pF | 5 |
| Average current consumption (4) | IDD4 |  | 1.18 | 2.8 | µA | VDD = 3 V; fSCL = 0 Hz, /INT = VDD, FOE = VDD, FOUT 32.768 kHz, CL = 0 pF | 5 |
| High-level input voltage | VIH |  |  | 5.5 | V | SCL, SDA, FOE pins; min printed 0.8 × VDD | 5 |
| Low-level input voltage | VIL | -0.3 |  |  | V | SCL, SDA, FOE pins; min printed GND - 0.3 (GND = 0 V); max printed 0.2 × VDD | 5 |
| High-level output voltage FOUT pin | VOH1 | 4.5 |  | 5 | V | VDD = 5 V, IOH = -1 mA | 5 |
| High-level output voltage FOUT pin | VOH2 | 2.2 |  | 3 | V | VDD = 3 V, IOH = -1 mA | 5 |
| High-level output voltage FOUT pin | VOH3 | 2.9 |  | 3 | V | VDD = 3 V, IOH = -100 µA | 5 |
| Low-level output voltage FOUT pin | VOL1 |  |  | 0.5 | V | VDD = 5 V, IOL = 1 mA; max printed GND + 0.5 (GND = 0 V) | 5 |
| Low-level output voltage FOUT pin | VOL2 |  |  | 0.8 | V | VDD = 3 V, IOL = 1 mA; max printed GND + 0.8 (GND = 0 V) | 5 |
| Low-level output voltage FOUT pin | VOL3 |  |  | 0.1 | V | VDD = 3 V, IOL = 100 µA; max printed GND + 0.1 (GND = 0 V) | 5 |
| Low-level output voltage /INT pin | VOL4 |  |  | 0.25 | V | VDD = 5 V, IOL = 1 mA; max printed GND + 0.25 (GND = 0 V) | 5 |
| Low-level output voltage /INT pin | VOL5 |  |  | 0.4 | V | VDD = 3 V, IOL = 1 mA; max printed GND + 0.4 (GND = 0 V) | 5 |
| Low-level output voltage SDA pin | VOL6 |  |  | 0.4 | V | VDD ≥ 2 V, IOL = 3 mA; max printed GND + 0.4 (GND = 0 V) | 5 |
| Input leakage current FOE, SCL, SDA | ILK | -0.5 |  | 0.5 | µA | VIN = VDD or GND | 5 |
| Output leakage current /INT, SDA, FOUT | IOZ | -0.5 |  | 0.5 | µA | VOUT = VDD or GND | 5 |
| SCL clock frequency | fSCL |  |  | 400 | kHz |  | 6 |
| Start condition setup time | tSU;STA | 0.6 |  |  | µs |  | 6 |
| Start condition hold time | tHD;STA | 0.6 |  |  | µs |  | 6 |
| Data setup time | tSU;DAT | 100 |  |  | ns |  | 6 |
| Data hold time | tHD;DAT | 0 |  |  | ns |  | 6 |
| Stop condition setup time | tSU;STO | 0.6 |  |  | µs |  | 6 |
| Bus idle time between start and stop condition | tBUF | 1.3 |  |  | µs |  | 6 |
| Time when SCL = L | tLOW | 1.3 |  |  | µs |  | 6 |
| Time when SCL = H | tHIGH | 0.6 |  |  | µs |  | 6 |
| Rise time for SCL and SDA | tr |  |  | 0.3 | µs |  | 6 |
| Fall time for SCL and SDA | tf |  |  | 0.3 | µs |  | 6 |
| Allowable spike time on bus | tSP |  |  | 50 | ns |  | 6 |
| Frequency/voltage characteristics | f/V | -1 |  | 1 | ppm | Ta = 25℃, VDD = 2.0 V to 5.5 V | 6 |
| Oscillation start time | tSTA |  |  | 0.5 | s | Ta = 25℃, VDD = 1.6 V to 5.5 V | 6 |
| Oscillation start time | tSTA |  |  | 1 | s | Ta = -40 to +85℃, VDD = 1.6 V to 5.5 V | 6 |
| Aging | fa | -3 |  | 3 | ppm | Ta = 25℃, VDD = 3.0 V, first year | 6 |
| Temperature sensor accuracy | Tsensor | -4 |  | 4 | ℃ | VDD = 3.0 V | 6 |
| FOUT duty | Duty | 40 | 50 | 60 | % | 50% of VDD level | 6 |
| Frequency stability (ordering table, FRTC8900S) | ∆f/f | -1.5 |  | 1.5 | ppm | Ta = 0 to +50℃, VDD = 3.0 V | 3 |
| Frequency stability (ordering table, FRTC8900S) | ∆f/f | -3 |  | 3 | ppm | Ta = -40 to +85℃, VDD = 3.0 V | 3 |
| Diode forward voltage | Vf |  | 0.6 |  | V | 1 mA | 23 |
| Diode forward voltage | Vf |  | 0.85 |  | V | 10 mA | 23 |
| On-resistance of Pch switch |  |  | 100 |  | ohm | VDD = 3.0 V, Ta = 25℃ | 23 |
| Diode reverse current | IR |  |  | 6 | nA | VDD = 5.5 V, -40 to 105℃ | 23 |

## CAD (KiCad official)

- Symbol: `FRTC8900S`
- Footprint: `Package_SO:SOIC-14_3.9x8.7mm_P1.27mm`
- 3D model: SOP-14 (KiCad packages3D, STEP)
- 3D model files: `frtc8900s-etched.step` / `frtc8900s-etched.glb` carry the MPN laser-etched on the die in a toggleable `Adom.LaserEtch` group (Fusion-ready); `frtc8900s.step` / `frtc8900s.glb` are the bare package body.

## Provenance

Data extracted from the manufacturer datasheet, not a distributor listing:

- **Datasheet:** [Nyfea datasheet](docs/frtc8900s-datasheet.pdf) (31 pp, sha256 `2a7da5dcf5cd5be1`, retrieved 2026-10-19, tier: lcsc)
- **Extractor:** parts-factory `2.0.0` / `extract_pins 0.3`, primary `claude-haiku-5-5` (text), consensus `claude-sonnet-5-5` (agreed), guards: pin_guards 0.1: passed. Pins are checked against the footprint pad set and their cited datasheet pages before publish.
- **CAD:** KiCad official libraries (CC-BY-SA 4.0).

[Datasheet PDF](docs/frtc8900s-datasheet.pdf)